公开(公告)号：JP2007173775A

公开(公告)日：2007-07-05

申请号：JP2006249779

申请日：2006-09-14

Applicant: Phoenix Precision Technology Corp ,  全懋精密科技股▲分▼有限公司

Inventor： WANG SHING-RU ,  WANG HSIEN-SHOU ,  HSU SHIH-PING

IPC: H05K3/46 ,  H01L23/12

Abstract: PROBLEM TO BE SOLVED: To provide a circuit board structure and its manufacturing method. SOLUTION: A carrier board is prepared, and then an insulating protective layer is formed over the carrier board, and then a plurality of openings are formed in the insulating protective layer to expose the carrier board. Then, a circuit structure is formed on the surface of the insulating protective layer and the openings, and further a dielectric layer is formed over the insulating protective layer and the circuit structure. Then a plurality of openings are formed in the dielectric layer to expose a part of the circuit structure, and then the carrier board is removed to form a coreless circuit board; thereby, the thickness of the circuit board is made smaller, and contribution can be made to the reduction in the size and improvement in the performance of a package product, and further, can cope with the requirement of miniaturization of electronic apparatuses. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种电路板结构及其制造方法。 解决方案：制备载体板，然后在载体板上形成绝缘保护层，然后在绝缘保护层中形成多个开口以露出载体板。 然后，在绝缘保护层和开口的表面上形成电路结构，并且在绝缘保护层和电路结构之上形成电介质层。 然后在电介质层中形成多个开口以露出电路结构的一部分，然后移除载体板以形成无芯电路板; 从而使电路板的厚度更小，并且能够减小封装产品的尺寸和提高性能，并且还可以应对电子设备的小型化的要求。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2009094128A

公开(公告)日：2009-04-30

申请号：JP2007260830

申请日：2007-10-04

Applicant: Phoenix Precision Technology Corp ,  全懋精密科技股▲分▼有限公司

Inventor： HSU SHIH-PING

IPC: H05K3/34

Abstract: PROBLEM TO BE SOLVED: To provide a circuit board required to use a fine-pitch distribution while avoiding a conductive element having a wing edge formed, and to provide a manufacturing method thereof.
SOLUTION: The circuit board includes a circuit board body having a plurality of electric connection pads on at least one surface, an insulating protection layer provided on a surface of the circuit board body and having openings, larger than the electric connection pads and not in contact with peripheral edges of the electric connection pads, corresponding to the electric connection pads, and solder materials provided on surfaces of the electric connection pads and having a smaller diameter than the electric connection pads, and then a fine-pitch electric connection structure is formed by forming the solder materials as conductive elements by solder reflowing and making them smaller than the openings of the insulating protection layer.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了提供使用细间距分布所需的电路板，同时避免形成有翼缘的导电元件，并提供其制造方法。 电路板包括电路板主体，其在至少一个表面上具有多个电连接焊盘，绝缘保护层设置在电路板主体的表面上并且具有大于电连接焊盘的开口， 不与电连接垫对应的电连接焊盘的周缘接触，以及设置在电连接焊盘的表面上并具有比电连接焊盘小的直径的焊料，然后是细间距电连接结构 通过焊料回流形成作为导电元件的焊料材料并使其小于绝缘保护层的开口而形成。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008171895A

公开(公告)日：2008-07-24

申请号：JP2007001768

申请日：2007-01-09

Applicant: Phoenix Precision Technology Corp ,  全懋精密科技股▲分▼有限公司

Inventor： CHANG CHIA-WEI ,  WENG LIN-YING ,  LAI ZAO-KUO ,  LIEN CHUNG-CHENG

IPC: H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a lamination structure of semiconductor element embedding supporting substrate wherein a module structure can be formed by embedding semiconductor elements in a supporting substrate, and to provide its manufacturing method.
SOLUTION: first and second supporting substrates 21a and 21b are provided, and at least one penetrating opening 211 is formed for each of the first and second supporting substrates 21a and 21b. First and second protective layers 22a and 22b are formed on the respective surfaces of the first and second supporting substrates, and at least one first semiconductor element 23a and one second semiconductor element 23b are arranged in the openings of the first and second substrates, respectively, and they are bonded to the first and second protective layers. A dielectric layer 24 is crimped between the surfaces of the first and second supporting substrates where the first and second protective layers are not formed, thus forming a module lamination structure.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种半导体元件嵌入支撑基板的层叠结构，其中可以通过将半导体元件嵌入支撑基板中而形成模块结构，并提供其制造方法。 解决方案：设置第一和第二支撑基板21a和21b，并且为第一和第二支撑基板21a和21b中的每一个形成至少一个贯通开口211。 第一和第二保护层22a和22b形成在第一和第二支撑衬底的各个表面上，并且至少一个第一半导体元件23a和一个第二半导体元件23b分别布置在第一和第二衬底的开口中， 并且它们被结合到第一和第二保护层。 在第一和第二支撑基板的没有形成第一和第二保护层的表面之间压接电介质层24，从而形成模块层叠结构。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008010705A

公开(公告)日：2008-01-17

申请号：JP2006180807

申请日：2006-06-30

Applicant: Phoenix Precision Technology Corp ,  全懋精密科技股▲分▼有限公司

Inventor： HSU SHIH-PING

IPC: H01L23/12

Abstract: PROBLEM TO BE SOLVED: To provide a package structure of a chip built-in substrate for effectively positioning the semiconductor chip to a chip carrier. SOLUTION: The package structure of the chip built-in substrate comprises a carrier plate having a step-like opening, the semiconductor chip (or the chip set) housed in the opening of the carrier plate; a dielectric layer formed to the semiconductor chip and the carrier plate, filled in a gap between the semiconductor chip and the opening of the carrier plate, and fixing the semiconductor chip to the carrier plate; and a circuit layer formed in the dielectric layer. The circuit layer is electrically connected to electrode pads of the semiconductor chip by a plurality of conductive structures, in the result, the semiconductor chip is electrically connected outside. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供用于有效地将半导体芯片定位到芯片载体的芯片内置基板的封装结构。 解决方案：芯片内置基板的封装结构包括具有阶梯状开口的承载板，容纳在承载板的开口中的半导体芯片（或芯片组）; 形成在半导体芯片和载体板上的电介质层，填充在半导体芯片和载体板的开口之间的间隙中，并将半导体芯片固定到载体板上; 以及形成在电介质层中的电路层。 电路层通过多个导电结构电连接到半导体芯片的电极焊盘，结果半导体芯片电连接到外部。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007053360A

公开(公告)日：2007-03-01

申请号：JP2006215065

申请日：2006-08-07

Applicant: Phoenix Precision Technology Corp ,  全懋精密科技股▲分▼有限公司

Inventor： HSU SHIH-PING

IPC: H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L23/5389 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/24227 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K1/185 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/043 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To provide the lamination structure of a semiconductor element-padding support plate, which embeds a semiconductor chip in a support plate so as to turn it into a modularized structure.
SOLUTION: A modularized structure is assembled in a three-dimensional assembly. The structure is equipped with: two support plates 21 which are each provided with at least an opening 21c and laminated into one piece by a joining layer 25; two semiconductor elements 22 which are fixed in the openings 21c of the support plates 21 respectively, and each provided with an active plane 22a where electrode pads 22c are provided; at least a dielectric layer 23 which is formed on the active plane 22a of the semiconductor element 22 and the surface 21a of the support plate 21, and equipped with at least a through-hole 26 located at a part corresponding to the electrode pad 22c; and at least a conductive structure 24a which is provided in the through-hole 26 of the dielectric layer 23, and electrically connects the circuit layer 24 that is formed on the surface of the dielectric layer 23 to the electric pad 22c of the semiconductor element 22.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供将半导体芯片嵌入支撑板中以将其变成模块化结构的半导体元件衬垫支撑板的层压结构。 解决方案：将模块化结构组装成三维组件。 该结构配备有：两个支撑板21，每个支撑板21至少设置有开口21c，并通过接合层25层压成一体; 两个半导体元件22分别固定在支撑板21的开口21c中，并且各自设置有设置有电极焊盘22c的有源平面22a; 至少形成在半导体元件22的有源平面22a和支撑板21的表面21a上的电介质层23，并且至少配置有位于对应于电极焊盘22c的部分的通孔26; 并且至少设置在电介质层23的通孔26中的导电结构体24a，并且将形成在电介质层23的表面上的电路层24电连接到半导体元件22的电焊盘22c 。版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007049154A

公开(公告)日：2007-02-22

申请号：JP2006215062

申请日：2006-08-07

Applicant: Phoenix Precision Technology Corp ,  全懋精密科技股▲分▼有限公司

Inventor： HSU SHIH-PING

IPC: H01L23/12 ,  H01L23/40 ,  H01L25/04 ,  H01L25/18

CPC classification number: H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To provide a chip embedded package structure and a manufacturing method therefor. SOLUTION: A support plate having at least one opening is prepared, a heat conduction block is formed at the opening of the support plate, a semiconductor chip is adhered to the heat conduction block, a dielectric layer and a circuit layer are sequentially formed on the support plate and semiconductor chip, and the circuit layer is electrically connected to the semiconductor chip, thus forming the chip embedded package structure. A heat dissipation layer is formed by providing the support plate with the heat conduction block. A combination of the support plate, heat conduction block and dielectric layer enables the avoidance of the warpage occurring in the subsequent manufacturing process, and the enhancement of the package structure quality. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种芯片嵌入式封装结构及其制造方法。 解决方案：制备具有至少一个开口的支撑板，在支撑板的开口处形成热传导块，半导体芯片粘附到导热块，电介质层和电路层依次 形成在支撑板和半导体芯片上，并且电路层电连接到半导体芯片，从而形成芯片嵌入封装结构。 通过向支撑板提供热传导块来形成散热层。 支撑板，导热块和电介质层的组合使得能够避免随后的制造过程中发生的翘曲以及包装结构质量的提高。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2009099730A

公开(公告)日：2009-05-07

申请号：JP2007269168

申请日：2007-10-16

Applicant: Phoenix Precision Technology Corp ,  全懋精密科技股▲フン▼有限公司

Inventor： SHIU SHR-BIN

IPC: H01L23/12

Abstract: PROBLEM TO BE SOLVED: To provide a solder ball arrangement-side surface structure of a package board used for preventing a conductive element located in the surface structure from falling by lack of bonding strength by increasing a contact area of the surface structure to stick the conductive element, and to provide a method of manufacturing the same. SOLUTION: The solder ball arrangement-side surface structure of a package board includes a chip arrangement side and a solder ball arrangement side facing each other on the package board, wherein first and second circuit layers are provided on the chip arrangement side and the solder ball arrangement side, respectively. A first insulation protective layer is formed on the chip arrangement side of the package board and the first circuit layer. The solder ball arrangement-side surface structure includes: a metal pad being part of the second circuit layer; a metal projecting edge circumferentially formed on the metal pad; and a second insulating protective layer located on the solder ball arrangement side of the package board, and having a second opening smaller than the outer diameter size of the metal projecting edge for exposing a partial surface of the metal projecting edge. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了提供用于防止位于表面结构中的导电元件的焊料球布置侧表面结构由于缺少接合强度而下降，通过将表面结构的接触面积增加到 粘贴导电元件，并提供其制造方法。 解决方案：封装板的焊球布置侧表面结构包括在封装板上彼此相对的芯片布置侧和焊球布置侧，其中第一和第二电路层设置在芯片布置侧， 焊锡球排列侧。 第一绝缘保护层形成在封装板和第一电路层的芯片布置侧上。 焊球布置侧表面结构包括：作为第二电路层的一部分的金属焊盘; 周边形成在金属垫上的金属突出边缘; 以及第二绝缘保护层，其位于所述封装板的所述焊球配置侧上，并且具有小于所述金属突出边缘的外径尺寸的第二开口，用于暴露所述金属突出边缘的部分表面。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009076851A

公开(公告)日：2009-04-09

申请号：JP2008116681

申请日：2008-04-28

Applicant: Phoenix Precision Technology Corp ,  フェニックス プレシジョン テクノロジー コーポレイション

Inventor： HSU SHI-PING

IPC: H01L21/60 ,  H05K1/02 ,  H05K3/18 ,  H05K3/24 ,  H05K3/34

CPC classification number: H01L24/81 ,  H01L23/498 ,  H01L23/49822 ,  H01L24/14 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/1403 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H05K3/062 ,  H05K3/108 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09736 ,  H05K2201/10674 ,  H05K2203/0361 ,  H05K2203/0369 ,  H05K2203/0574 ,  Y10T29/49165

Abstract: PROBLEM TO BE SOLVED: To provide a packaging substrate structure applicable to fine pitch formation of the packaging substrate structure and quality improvement of an under filling process, capable of solving a connection failure caused by nonuniform solder bumps, and of improving reliability of a product, and manufacturable at economical cost; and a method for manufacturing the same. SOLUTION: This invention relates to a packaging substrate and a method for manufacturing the same. The packaging substrate includes: a substrate body, wherein a surface thereof has a circuit layer comprising a plurality of circuits and a plurality of conductive pads, and the conductive pads are higher than the circuits; and an insulating protection layer disposed on the surface of the substrate body, wherein the insulating protection layer has a plurality of openings exposing the conductive pads, and the size of the openings is larger than or equal to that of the conductive pads. Accordingly, the packaging substrate structure of the invention can be employed in a fine-pitch flip-chip packaging structure. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了提供适用于包装基板结构的细间距形成和填充过程的质量改进的封装基板结构，能够解决由不均匀的焊料凸块引起的连接故障，并且提高可靠性 一种产品，经济实惠; 及其制造方法。 解决方案：本发明涉及一种封装基板及其制造方法。 封装基板包括：基板主体，其表面具有包括多个电路和多个导电焊盘的电路层，并且导电焊盘高于电路; 以及设置在所述基板主体的表面上的绝缘保护层，其中所述绝缘保护层具有暴露所述导电焊盘的多个开口，并且所述开口的尺寸大于或等于所述导电焊盘的尺寸。 因此，本发明的封装基板结构可以用于细间距倒装芯片封装结构。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008193068A

公开(公告)日：2008-08-21

申请号：JP2008002565

申请日：2008-01-09

Applicant: Phoenix Precision Technology Corp ,  全懋精密科技股▲フン▼有限公司

Inventor： SHIU SHR-BIN

IPC: H01L23/12

CPC classification number: H05K3/243 ,  H01L23/49811 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H05K3/108 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0574 ,  H01L2224/05599

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor package substrate structure that is electrically connected to a semiconductor chip with ease, and ensures quality and reliability of a subsequent packaging process. SOLUTION: A semiconductor package substrate structure comprises: a circuit board that has multiple first electrical connection pads formed on at least one surface thereof; conductive posts that are formed on the surfaces of the first electrical connection pads; and an insulating protective layer that is formed on the surface of the circuit board and has openings formed to completely expose the conductive posts. In the semiconductor package substrate structure, the conductive posts protrude from the surface of the insulating protective layer. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供与半导体芯片电连接的半导体封装基板结构，并确保后续封装工艺的质量和可靠性。 解决方案：半导体封装基板结构包括：电路板，其具有形成在其至少一个表面上的多个第一电连接焊盘; 导电柱，其形成在第一电连接焊盘的表面上; 以及形成在电路板的表面上并具有形成为完全暴露导电柱的开口的绝缘保护层。 在半导体封装基板结构中，导电柱从绝缘保护层的表面突出。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2009099799A

公开(公告)日：2009-05-07

申请号：JP2007270382

申请日：2007-10-17

Applicant: Phoenix Precision Technology Corp ,  全懋精密科技股▲フン▼有限公司

Inventor： SHIU SHR-BIN

IPC: H01L23/12

CPC classification number: H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To achieve high-density wiring and fine pitch without arranging an electrically-plated conductor, to improve a bonding property to a gold wire of wire bonding junction, and to respond to usage of a high pin number of a fine pitch. SOLUTION: A package board includes: two facing chip arrangement side and solder ball arrangement side; a plurality of wire bonding pads 401 and a plurality of solder ball pads 402 on the respective sides; and a first insulation protective layer and a second insulation protective layer on the chip arrangement side and the solder ball arrangement side, respectively. The package board includes: a board body on which a plurality of first openings and a plurality of second openings for exposing the wire bonding pads and the solder ball pads are opened on the first and second insulation protective layers, respectively; chemically-plated metal layers 42 formed on the surfaces of the wire bonding pads and the solder ball pads; and a wire bonding metal layer 45 formed on the surface of the chemically-plated metal layer 42 on the wire bonding pads. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了实现高密度布线和细间距而不布置电镀导体，改善与引线接合点的金线的接合性能，并且响应于使用高引脚数 一个很好的音调。 解决方案：封装板包括：两个面对的芯片布置侧和焊球布置侧; 多个引线接合垫401和相应侧上的多个焊球402; 以及分别在芯片布置侧和焊球配置侧的第一绝缘保护层和第二绝缘保护层。 所述封装板包括：分别在所述第一绝缘保护层和所述第二绝缘保护层上分别开有多个第一开口和用于暴露所述引线接合焊盘和所述焊球垫的多个第二开口的板体; 形成在引线接合焊盘和焊球垫的表面上的化学镀金属层42; 以及形成在引线接合焊盘上的化学镀金属层42的表面上的引线接合金属层45。 版权所有（C）2009，JPO＆INPIT