公开(公告)号：US20050001295A1

公开(公告)日：2005-01-06

申请号：US10852632

申请日：2004-05-24

Applicant: Jerrold King ,  J. Brooks ,  Walter Moden

Inventor： Jerrold King ,  J. Brooks ,  Walter Moden

IPC: H01L23/31 ,  H01L23/495 ,  H01L21/44

CPC classification number: H01L23/3142 ,  H01L23/4951 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/1815 ,  Y10S438/926 ,  Y10S438/928 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor die includes a metal layer deposited thereon for enhancing adhesion between the die and a mold compound package. The metal layer is substantially oxide free. The die is coated with a layer or layers of copper (Cu) and/or palladium (Pd) by electroplating or electroless coating techniques. The metal layer provides a uniform wetting surface for better adhesion of the die with the mold compound package during encapsulation. The increased adhesion reduces the delamination potential of the die from the package.

Abstract translation: 半导体管芯包括沉积在其上的金属层，用于增强管芯和模具复合封装之间的附着力。 金属层基本上不含氧化物。 通过电镀或无电涂覆技术将模具涂覆有一层或多层铜（Cu）和/或钯（Pd）。 金属层提供均匀的润湿表面，用于在封装期间模具与模具复合包装的更好的附着。 增加的粘附力降低了模具从包装中的分层势。

公开(公告)号：US6046496A

公开(公告)日：2000-04-04

申请号：US964091

申请日：1997-11-04

Applicant: David Corisis ,  Walter Moden

Inventor： David Corisis ,  Walter Moden

IPC: H01L23/433 ,  H01L23/495 ,  H01L23/28

CPC classification number: H01L23/49568 ,  H01L23/4334 ,  H01L2924/0002

Abstract: The present invention relates to a heat management structure within a chip package that allows for heat rejection away from a chip but that avoids the prior art problems of thermal stresses caused by dissimilar thermal conductivities of a heat management structure and of creating a thermally unbalanced package due to disparate distribution of packaging plastic. In an embodiment of the present invention a package includes a chip, leads on the chip, a die attach, a downset, a packaging plastic, and an outer structure among others. The outer structure, downset, and die attach are together a substantially unitary article. Achieving a balanced package that substantially resists warpage and bowing during ordinary manufacture and ordinary use in the life of the package is accomplished by balancing packaging material width and the ability of the downset to resist warpage and bowing stresses. A substantial portion of the outer structure is exposed to the external part of the package in the surface which includes the packaging lower edge. Alternatively, the downset can include a part of the external boundary of the package such that exposure of the downset to the external portion of the package allows for additional heat rejection away from the chip in addition to the use of the outer structure.

Abstract translation: 本发明涉及一种芯片封装内的热管理结构，其允许远离芯片的散热，但是避免了由热管理结构的不同热导率引起的热应力的现有技术问题，并且产生了热不平衡的封装 包装塑料分布不均匀。 在本发明的一个实施例中，封装包括芯片，芯片上的引线，管芯附接，压封，封装塑料和外部结构等。 外部结构，底部和管芯附着在一起是基本上一体的制品。 通过平衡包装材料宽度和降低翘曲和弯曲应力的能力，实现了在包装寿命期间普遍制造和普通使用中基本抵抗翘曲和弯曲的平衡包装。 外部结构的主要部分在包括封装下边缘的表面中暴露于封装的外部部分。 可替换地，下降装置可以包括包装的外部边界的一部分，使得除了外部结构的使用之外，向下的封装暴露于封装的外部部分还允许远离芯片的额外的散热。

公开(公告)号：US07215015B2

公开(公告)日：2007-05-08

申请号：US10899258

申请日：2004-07-26

Applicant: Walter Moden

Inventor： Walter Moden

IPC: H01L23/02

CPC classification number: H01L27/14634 ,  H01L21/563 ,  H01L23/3185 ,  H01L24/28 ,  H01L24/31 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/86 ,  H01L27/14643 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/48747 ,  H01L2224/73203 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83951 ,  H01L2224/8592 ,  H01L2224/92125 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/00014 ,  H01L2224/48744 ,  H01L2924/00

Abstract: A semiconductor package includes a substrate, and a semiconductor die flip chip mounted to the substrate. The package also includes substrate circuitry on a circuit side of the substrate, die circuitry on a back side of the die, terminal contacts on the die circuitry, bonded connections between the substrate circuitry and the die circuitry, and an encapsulant on the bonded connections and edges of the die. The die can include an image sensor on the circuit side configured to receive electromagnetic radiation transmitted through the substrate. A method for fabricating the package includes the step of providing a wafer with multiple dice, forming the die circuitry on the dice, and simulating the wafer into individual dice. The method also includes the steps of providing a substrate panel with multiple substrates, forming the substrate circuitry on the substrates, flip chip bonding the dice to the substrates, forming bonded connections between the dice and the substrates, forming the terminal contacts on the die circuitry, and singulating the panel into separate components.

Abstract translation: 半导体封装包括衬底和安装到衬底的半导体管芯倒装芯片。 封装还包括在衬底的电路侧上的衬底电路，裸片的背面上的裸片电路，裸片电路上的端子触点，衬底电路和裸片电路之间的结合连接，以及粘合连接上的密封剂 模具边缘。 芯片可以包括在电路侧的图像传感器，其配置为接收透射通过基板的电磁辐射。 制造封装的方法包括以下步骤：提供具有多个裸片的晶片，在裸片上形成裸片电路，以及将晶片模拟成单独的裸片。 该方法还包括以下步骤：向衬底面板提供多个衬底，在衬底上形成衬底电路，将裸片倒装芯片接合到衬底，在裸片与衬底之间形成接合连接，在裸片电路上形成端子触点 ，并将面板分成单独的组件。

公开(公告)号：US07065868B2

公开(公告)日：2006-06-27

申请号：US10747333

申请日：2003-12-29

Applicant: Larry Kinsman ,  Mike Brooks ,  Warren M. Farnworth ,  Walter Moden ,  Terry Lee

Inventor： Larry Kinsman ,  Mike Brooks ,  Warren M. Farnworth ,  Walter Moden ,  Terry Lee

IPC: H01R9/00

CPC classification number: H05K7/1415 ,  B25B27/00 ,  H05K3/301 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49169 ,  Y10T29/49208 ,  Y10T29/49222 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53183 ,  Y10T29/53191 ,  Y10T29/53209 ,  Y10T29/53257 ,  Y10T29/53261 ,  Y10T29/53265

Abstract: A method is provided for installing circuit components, such as memory devices, in a support, such as a socket. The device to be installed is supported in a holder or shell. The holder is positioned over a support region in the receiving socket. A manual actuator is pressed into the holder to eject the device from the holder and to install the device in the support. The holder may be configured to hold a single device, or multiple devices aligned in slots defined by partitions. A multi-device tray may be provided for indexing devices toward an ejection slot, through which the devices are installed by manual actuation of an ejecting actuator. The technique provides protection for the device prior to and during installation, and facilitates manual installation of such devices without requiring direct hand contact with the device either prior to or during installation.

Abstract translation: 提供了一种用于将电路组件（诸如存储器件）安装在诸如插座的支撑件中的方法。 要安装的设备支撑在支架或外壳中。 保持器定位在接收插座中的支撑区域上方。 将手动执行器压入保持器中以将装置从保持器中排出并将装置安装在支撑件中。 保持器可以被配置为保持单个设备，或者多个设备在由分区定义的槽中对齐。 可以提供多装置托盘用于将装置向分度装置移动到排出槽，通过这些装置通过手动驱动排放致动器来安装装置。 该技术在安装之前和安装期间为设备提供保护，并且便于手动安装这些设备，而不需要在安装之前或安装期间直接与设备接触。

公开(公告)号：US20060060957A1

公开(公告)日：2006-03-23

申请号：US11263509

申请日：2005-10-31

Applicant: David Corisis ,  Walter Moden ,  Leonard Mess ,  Larry Kinsman

Inventor： David Corisis ,  Walter Moden ,  Leonard Mess ,  Larry Kinsman

IPC: H01L23/02 ,  H01L21/50

CPC classification number: H01L24/06 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/145 ,  H05K3/222 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays. The ball grid array packages comprise flexible or rigid substrates. The ball grid array packages additionally comprise an arrangement for the substantial matching of impedance for the circuits connected to the semiconductor devices.

公开(公告)号：US20050218486A1

公开(公告)日：2005-10-06

申请号：US10797647

申请日：2004-03-10

Applicant: Michael Morrison ,  Walter Moden ,  Corey Jacobsen

Inventor： Michael Morrison ,  Walter Moden ,  Corey Jacobsen

IPC: H01L23/31 ,  H01L23/36 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L21/00 ,  B33Y80/00 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49109 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A semiconductor device assembly and method of making the devices are disclosed. The assembly comprises a semiconductor die attached to an electrically conductive layer, which is in turn, connected to a dielectric layer carrying conductive traces of the electrical connection layer. The conductive traces provide connection between an array of discrete conductive elements and bonding wires connected to bond pads of the die. The conductive layer enhances thermal conduction and structural stiffness for the assembly. In addition, the conductive layer provides a voltage reference plane that may be connected to a power source, a ground source, or an intermediate reference voltage. The conductive layer also includes at least one electrical current isolation slot, which segments the conductive layer to help isolate noise induced in one segment of the conductive layer from the other segments.

Abstract translation: 公开了半导体器件组件及其制造方法。 组件包括附接到导电层的半导体管芯，该半导体管芯又连接到承载电连接层的导电迹线的电介质层。 导电迹线提供分立的导电元件的阵列与连接到管芯的接合焊盘的接合线之间的连接。 导电层增强了组件的热传导和结构刚度。 此外，导电层提供可以连接到电源，接地源或中间参考电压的电压参考平面。 导电层还包括至少一个电流隔离槽，其分割导电层以帮助将导电层的一个区段中感应的噪声与其它区段隔离。

公开(公告)号：US20050167850A1

公开(公告)日：2005-08-04

申请号：US11070364

申请日：2005-03-01

Applicant: Walter Moden

Inventor： Walter Moden

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/13 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H05K1/14 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36 ,  H01L21/48

CPC classification number: H01L24/81 ,  H01L21/485 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5382 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/85 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19107 ,  H05K1/141 ,  H05K3/305 ,  H05K3/328 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/049 ,  H05K2201/10477 ,  H05K2201/10727 ,  H05K2203/0415 ,  H05K2203/049 ,  Y02P70/613 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A board for connecting a bare semiconductor die with a bond pad arrangement which does not conform to a master printed circuit board with a specific or standardized pin out, connector pad, or lead placement arrangement. The board comprises a printed circuit board including first elements, such as minute solder balls, pins, or bond wires, for making electrical contact between the board and the master board, and second elements, such as minute solder balls, pins, or bond wires, for making electrical contact between the semiconductor die and the board. The board has circuit traces for electrical communication between the board/master board electrical contact elements, and the semiconductor die board electrical contact elements.

Abstract translation: 用于将裸半导体管芯与不符合具有特定或标准的引脚输出，连接器焊盘或引线放置布置的主印刷电路板的接合焊盘装置连接的板。 板包括印刷电路板，其包括第一元件，例如用于在基板和母板之间进行电接触的微小焊球，引脚或接合线，以及第二元件，例如微小的焊球，引脚或接合线 用于在半导体管芯和电路板之间进行电接触。 电路板具有用于电路板/主板电接触元件之间的电气通信的电路迹线以及半导体裸片板电接触元件。

公开(公告)号：US06681480B1

公开(公告)日：2004-01-27

申请号：US09258764

申请日：1999-02-26

Applicant: Larry Kinsman ,  Mike Brooks ,  Warren M. Farnworth ,  Walter Moden ,  Terry Lee

Inventor： Larry Kinsman ,  Mike Brooks ,  Warren M. Farnworth ,  Walter Moden ,  Terry Lee

IPC: B23P1900

CPC classification number: H05K7/1415 ,  B25B27/00 ,  H05K3/301 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49169 ,  Y10T29/49208 ,  Y10T29/49222 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53183 ,  Y10T29/53191 ,  Y10T29/53209 ,  Y10T29/53257 ,  Y10T29/53261 ,  Y10T29/53265

Abstract: A technique is provided for installing circuit components, such as memory devices, in a support, such as a socket. The device to be installed is supported in a holder or shell. The holder is positioned over a support region in the receiving socket. A manual actuator is pressed into the holder to eject the device from the holder and to install the device in the support. The holder may be configured to hold a single device, or multiple devices aligned in slots defined by partitions. A multi-device tray may be provided for indexing devices toward an ejection slot, through which the devices are installed by manual actuation of an ejecting actuator. The technique provides protection for the device prior to and during installation, and facilitates manual installation of such devices without requiring direct hand contact with the device either prior to or during installation.

Abstract translation: 提供了一种技术，用于将诸如存储设备的电路组件安装在诸如插座的支撑件中。 要安装的设备支撑在支架或外壳中。 保持器定位在接收插座中的支撑区域上方。 将手动执行器压入保持器中以将装置从保持器中排出并将装置安装在支撑件中。 保持器可以被配置为保持单个设备，或者多个设备在由分区定义的槽中对齐。 可以提供多装置托盘用于将装置向分度装置移动到排出槽，通过这些装置通过手动驱动排放致动器来安装装置。 该技术在安装之前和安装期间为设备提供保护，并且便于手动安装这些设备，而不需要在安装之前或安装期间直接与设备接触。

公开(公告)号：US06625885B1

公开(公告)日：2003-09-30

申请号：US09511692

申请日：2000-02-23

Applicant: Walter Moden

Inventor： Walter Moden

IPC: H01R4300

CPC classification number: H01R13/2435 ,  H01R13/2442 ,  H01R13/405 ,  H01R43/24 ,  Y10T29/49121 ,  Y10T29/4914 ,  Y10T29/49146 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49222 ,  Y10T29/53178 ,  Y10T29/53183

Abstract: The invention provides a method of forming an electrical contact device and a pre-assembly for producing the electrical contact device. The electrical contact device is formed by providing a conducting frame and an insulating frame which is added to predetermined portions of the conducting frame to form the pre-assembly. A plurality of fine pitch electrical leads are disposed in parallel spaced apart relation and connected to each other by connecting strips. An insulating material is applied to the conducting frame to form the insulating frame. The insulating frame encapsulates portions of the electrical leads which extend from opposite sides of the center of the insulating frame retaining, therefore, the electrical leads in position and electrically isolated from one another. Portions of the conducting frame are then removed from the pre-assembly to obtain the electrical device.

Abstract translation: 本发明提供一种形成电接触装置的方法和用于产生电接触装置的预组件。 电接触装置通过提供导电框架和绝缘框架形成，绝缘框架被附加到导电框架的预定部分以形成预组件。 多个细间距电引线以平行间隔的关系设置，并通过连接带彼此连接。 将绝缘材料施加到导电框架以形成绝缘框架。 绝缘框架封装从绝缘框架的中心的相对侧延伸的电引线的部分，因此将电引线保持就位并且彼此电隔离。 然后将导电框架的部分从预组件移除以获得电气装置。

公开(公告)号：US06589810B1

公开(公告)日：2003-07-08

申请号：US09546706

申请日：2000-04-10

Applicant: Walter Moden

Inventor： Walter Moden

IPC: H01L2144

CPC classification number: H01L23/49838 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/4951 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16237 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10161 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A BGA package and a method for fabricating the package are provided. The package includes a semiconductor die, internal conductors wire bonded to bond pads on the die, external ball contacts attached to ball bonding pads formed on the conductors in a dense grid pattern, and an encapsulating resin encapsulating the die and conductors. The package is fabricated using a lead frame having lead fingers that form the conductors. The die is back bonded to a polymer tape placed across the lead fingers, and then wire bonded to bonding pads on the conductors. In addition, the encapsulating resin is molded to include openings for the ball contacts which are aligned with the ball bonding pads. An alternate embodiment BGA package includes a polymer substrate adhesively bonded to a face of the die. The polymer substrate includes conductors having beam leads aligned with an opening through the polymer substrate. The opening provides access for a bonding tool for bonding bumps on the beam leads to bond pads on the die.