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公开(公告)号：KR1020110048231A
公开(公告)日：2011-05-11
申请号：KR1020090104939
申请日：2009-11-02
Applicant: 삼성전기주식회사 , 고려대학교 산학협력단
IPC: H03M1/38
CPC classification number: H03M1/1215 , H03M1/46
Abstract: PURPOSE: A successive approximation analog/digital converter and a time-interleaved successive approximation analog/digital converter are provided to working speed thereof by reducing an operation clock in one cycle. CONSTITUTION: A sample and hold part(11) samples the size of an analog input signal by using one cycle of a clock signal. A first comparison unit(12) compares the size and comparative object voltage of the analog input signal every one cycle of clock. A second comparison unit(15) compares the size of the sampled input signal with half of the preset reference voltage. A successive approximation register block(13) determines the value of the most significant bit of the transformed digital value according to the comparison result of the second comparison unit. A digital to analog converter(14) generates comparative object voltage.
Abstract translation: 目的：通过在一个周期内减少操作时钟，为其工作速度提供逐次逼近的模拟/数字转换器和时间交错的逐次逼近模拟/数字转换器。 构成：采样和保持部分（11）通过使用一个时钟信号周期对模拟输入信号的大小进行采样。 第一比较单元（12）每一个时钟周期比较模拟输入信号的尺寸和比较对象电压。 第二比较单元（15）将采样输入信号的大小与预设参考电压的一半进行比较。 逐次逼近寄存器块（13）根据第二比较单元的比较结果来确定经变换的数字值的最高有效位的值。 数模转换器（14）产生比较对象电压。
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公开(公告)号：KR1020100067466A
公开(公告)日：2010-06-21
申请号：KR1020080126042
申请日：2008-12-11
Applicant: 삼성전기주식회사
Inventor： 정찬용
CPC classification number: H03M3/402 , H03M1/12 , H03M3/458 , H03M2201/196
Abstract: PURPOSE: A converter and a wireless telecommunications system using the same are provided to possessively process a signal for various frequency signals of inputs by controlling a sampling frequency offered to a sigma-delta modulator according to an analog input signal. CONSTITUTION: A converter(200) includes a band pass, a sigma-delta modulator(210) and a detector(220). The sigma-delta modulator outputs a digital frequency signal by sigma-delta-modulating an analog signal using a received set sampling frequency. The detector senses a band of the analog signal. The detector supplies the sampling frequency to the sigma-delta modulator according to the detected signal. The detector includes a frequency-voltage converter(221) for changing the frequency of the analog signal into the voltage, an analog-digital converter(222) for changing the voltage into the digital signal and a clock control part(223) for adjusting the sampling frequency.
Abstract translation: 目的：通过根据模拟输入信号控制提供给Σ-Δ调制器的采样频率，提供了一种转换器和使用该转换器和无线电信系统来对输入的各种频率信号进行信号处理。 构成：A转换器（200）包括带通，Σ-Δ调制器（210）和检测器（220）。 Σ-Δ调制器通过使用接收的设定采样频率对模拟信号进行Σ-Δ调制来输出数字频率信号。 检测器检测模拟信号的频带。 检测器根据检测到的信号将采样频率提供给Σ-Δ调制器。 检测器包括用于将模拟信号的频率改变为电压的频率 - 电压转换器（221），用于将电压改变为数字信号的模数转换器（222）和用于调整电压的时钟控制部分（223） 采样频率。
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公开(公告)号：KR100449631B1
公开(公告)日：2004-09-22
申请号：KR1020020034746
申请日：2002-06-21
Applicant: 삼성전기주식회사
IPC: H03B5/32
CPC classification number: H03B5/366
Abstract: The present invention relates to a multiple output crystal oscillator having a plurality of output terminals for implementing multiple output and Integrated Circuit (IC) chips. More particularly, the crystal oscillator comprises a crystal resonator, a first IC chip having an oscillating circuit block and a frequency-adjusting circuit block, a second IC chip having an output-adjusting block, and a substrate structure for mounting said first and second IC chips, wherein said output terminals include a basic output terminal for outputting the oscillating signal from said first IC chip and at least one additional output terminal for outputting at least one wave form-adjusted oscillation signal from said second IC chip. In the present invention, said basic output terminal is placed on one of four underside corners of said substrate, and said additional output terminal is placed on the portion of the underside except the corners.
Abstract translation: 本发明涉及具有用于实现多输出和集成电路（IC）芯片的多个输出端子的多输出晶体振荡器。 更具体地说，晶体振荡器包括晶体谐振器，具有振荡电路块和频率调节电路块的第一IC芯片，具有输出调节块的第二IC芯片以及用于安装所述第一和第二IC 芯片，其中所述输出端子包括用于输出来自所述第一IC芯片的振荡信号的基本输出端子和用于从所述第二IC芯片输出至少一个波形调整后的振荡信号的至少一个附加输出端子。 在本发明中，所述基本输出端子被放置在所述衬底的四个下侧拐角中的一个上，并且所述附加输出端子被放置在除拐角之外的下侧部分上。
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公开(公告)号：KR1020030045409A
公开(公告)日：2003-06-11
申请号：KR1020010076124
申请日：2001-12-04
Applicant: 삼성전기주식회사
Inventor： 정찬용
IPC: H03L1/02
CPC classification number: H03L1/028
Abstract: PURPOSE: A temperature compensated crystal oscillator is provided to reduce the height of the products by providing a structure formed by opening a pair of cavities up and down to mount the crystal oscillator and an integrated circuit(IC) chip and not overlapping the two cavity in a vertical direction so as to omit the substrate to divide the crystal oscillator and the IC chip. CONSTITUTION: A temperature compensated crystal oscillator includes a first substrate structure(41) made of at least one substrate and formed thereon a cavity, a second substrate structure(42), made of at least one substrate, placed on the top of the first substrate structure and not overlapped with the cavity of the first substrate structure(41), an integrated circuit(IC) chip(47) mounted on the cavity of the first substrate structure(41), a crystal oscillator(43) mounted on the cavity of the second substrate structure(42), a molding part(49) having a plane below the first substrate structure(41) by filling the cavity with a resin and a metal cover(45) for covering the cavity formed on the first substrate structure(41).
Abstract translation: 目的：提供一种温度补偿晶体振荡器，通过提供通过上下打开一对空腔而形成的结构来降低产品的高度，以安装晶体振荡器和集成电路（IC）芯片，并且不与两个腔体重叠 垂直方向，以省略基板以分离晶体振荡器和IC芯片。 构成：温度补偿晶体振荡器包括由至少一个衬底制成并在其上形成的空腔的第一衬底结构（41），由至少一个衬底制成的第二衬底结构（42），放置在第一衬底的顶部 结构并且不与第一基板结构（41）的空腔重叠，安装在第一基板结构（41）的空腔上的集成电路（IC）芯片（47），安装在第一基板结构 第二基板结构（42），通过用树脂填充空腔而具有在第一基板结构（41）下方的平面的模制部件（49）和用于覆盖形成在第一基板结构上的空腔的金属盖（45） 41）。
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Patent Agency Ranking
公开(公告)号：KR101616597B1
公开(公告)日：2016-04-28
申请号：KR1020120134539
申请日：2012-11-26
Applicant: 삼성전기주식회사
Inventor： 정찬용
IPC: H03K17/687 , H04B1/48
CPC classification number: H03K17/693 , H03K17/102
Abstract: 본발명은고주파스위치에관한것이다. 본발명의고주파스위치는복수의제1 스위치소자및 상기복수의제1 스위치소자의제어단에각각연결되는적어도하나의제1 다이오드소자를구비하여, 제1 고주파신호를송수신하는공통포트와상기제1 고주파신호를입출력하는제1 포트사이를도통또는차단하는제1 신호전달부; 및복수의제2 스위치소자및 상기복수의제2 스위치소자의제어단에각각연결되는적어도하나의제2 다이오드소자를구비하여, 제2 고주파신호를송수신하는상기공통포트및 상기제2 고주파신호를입출력하는제2 포트사이를도통또는차단하는제2 신호전달부; 를포함할수 있다.
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公开(公告)号：KR1020150005347A
公开(公告)日：2015-01-14
申请号：KR1020130079201
申请日：2013-07-05
Applicant: 삼성전기주식회사
Inventor： 정찬용
CPC classification number: H03F1/0227 , H03F3/24
Abstract: 본 발명은 전원 공급부; 상기 전원 공급부로부터 전원을 공급받고, 송신 신호에 기초한 포락선 정보를 획득하고, 상기 포락선 정보에 근거하여 포락선 전원을 획득하는 포락선 트랙킹 모듈; 상기 전원 공급부 및 상기 포락선 트랙킹 모듈 중 어느 하나로부터 전원을 공급받고, 송신 신호를 증폭하는 송신 신호 증폭기; 및 상기 포락선 트랙킹 모듈의 비안정화 구간인 제1 구간에는 상기 전원 공급부와 상기 송신 신호 증폭기를 연결하고, 상기 포락선 트랙킹 모듈의 안정화 구간인 제2 구간에는 상기 포락선 트랙킹 모듈과 상기 송신 신호 증폭기를 연결하는 스위칭부;를 포함하는 포락선 트랙킹 전원 장치에 관한 것이다.
Abstract translation: 本发明涉及一种包络跟踪电源装置，包括：电源单元; 从所述电源单元接收源电压的信封跟踪模块，基于发送信号取得信封信息，并且基于所述信封信息取得信封源; 传输信号放大器，其从电源单元和包络跟踪模块之一接收源电压并放大发送信号; 以及切换单元，其在第一周期期间，当所述包络跟踪模块不稳定时，将所述电源单元与所述发送信号放大器耦合，并且在所述包络跟踪模块期间将所述包络跟踪模块与所述发送信号放大器耦合 稳定了
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公开(公告)号：KR1020140086471A
公开(公告)日：2014-07-08
申请号：KR1020120157019
申请日：2012-12-28
Applicant: 삼성전기주식회사
IPC: H03K17/687 , H03H7/38 , H01G7/00 , H04B1/16
Abstract: The present invention relates to a variable capacitance circuit. According to the present invention, disclosed is a variable capacitance circuit which comprises multiple capacitance circuit parts including at least one switched capacitor unit connected in parallel respectively between a first terminal and a second terminal where a signal is inputted and outputted to provide capacitance; and a switch module having multiple switches stacked between the second terminal and a first ground terminal, wherein the switched capacitor unit comprises a switch part switching a forming path of the capacitance; and a capacitor part providing the capacitance through the path formed according to the switching of the switch part.
Abstract translation: 本发明涉及可变电容电路。 根据本发明，公开了一种可变电容电路，其包括多个电容电路部分，包括至少一个开关电容器单元，分别并联在第一端子和第二端子之间，其中输入和输出信号以提供电容; 以及开关模块，其具有堆叠在所述第二端子和第一接地端子之间的多个开关，其中所述开关电容器单元包括切换所述电容的形成路径的开关部件; 以及电容器部，其通过根据开关部的切换而形成的路径提供电容。
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公开(公告)号：KR1020140017384A
公开(公告)日：2014-02-11
申请号：KR1020120084473
申请日：2012-08-01
Applicant: 삼성전기주식회사
IPC: H03K17/687 , H03H7/38 , H01G7/00
CPC classification number: H03K3/012 , H03J3/20 , H03J2200/10
Abstract: The present invention relates to a variable capacitance control circuit and a variable capacitance control method by the variable capacitance control circuit including an MIM capacitor, multiple FET switches, and a control unit. The variable capacitance control method of the present invention obtains a desired variable capacitance value by outputting a control signal which turns on an FET among the multiple (n number) FET switches and turns off remaining (n-1) FET switches by the control unit to multiple FET switches. The present invention increases a Q value (Q=1/RC) by reducing an overall FET on-resistance value by using a control way which turns on an FET switch among the N number of FET switches and turns off remaining FET switches and thereby optimizes power consumption in a power amplifier (PA) and a reception rate in a low noise amplifier (LNA). [Reference numerals] (AA) (n-1) number
Abstract translation: 本发明涉及一种包括MIM电容器，多个FET开关和控制单元的可变电容控制电路的可变电容控制电路和可变电容控制方法。 本发明的可变电容控制方法通过输出在多个（n个）FET开关中导通FET的控制信号，并且通过控制单元将剩余的（n-1）个FET开关截止，从而获得期望的可变电容值 多个FET开关。 本发明通过使用在N个FET开关中导通FET开关并且关闭剩余FET开关的控制方式来降低总FET导通电阻值来增加Q值（Q = 1 / RC），从而优化 功率放大器（PA）中的功耗和低噪声放大器（LNA）中的接收速率。 （标号）（AA）（n-1）数
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30.发明公开
公开(公告)号：KR1020130109408A
公开(公告)日：2013-10-08
申请号：KR1020120031120
申请日：2012-03-27
Applicant: 삼성전기주식회사
Inventor： 정찬용
Abstract: PURPOSE: A hybrid variable capacity, an RF device, a hybrid variable capacitor manufacturing method, and a variable capacitor adjustment method are provided to increase the tuning range and reduce the step size, thereby enhancing the resolution and enabling fine tuning. CONSTITUTION: A hybrid variable capacitor includes a metal insulator metal (MIM) cap array, an MOS varactor (30), and a FET switch (20). The MIM cap array includes MIM capacitors and has the varied capacitance corresponding to the value of a lower bit domain among digital values of the capacitance to be adjusted. The MOS varactor is connected to the MIM cap array in parallel and has the varied capacitance corresponding to the value of an upper bit domain among the digital values. The FET switch is connected to each capacitor of the MIM cap array and performs switching depending on the value of the lower bit domain to make the MIM cap array have the varied capacitance. [Reference numerals] (AA) Lower bit area; (BB) Upper bit area
Abstract translation: 目的：提供混合可变容量，RF器件，混合可变电容器制造方法和可变电容器调节方法，以增加调谐范围并减小步长，从而提高分辨率并实现微调。 构成：混合可变电容器包括金属绝缘体金属（MIM）帽阵列，MOS可变电抗器（30）和FET开关（20）。 MIM帽阵列包括MIM电容器，并且具有对应于要调节的电容的数字值中较低位域的值的变化的电容。 MOS变容管并联连接到MIM帽阵列，并且具有与数字值中的较高位域的值相对应的变化的电容。 FET开关连接到MIM帽阵列的每个电容器，并根据低位域的值执行切换，以使MIM帽阵列具有变化的电容。 （标号）（AA）下位区; （BB）高位区域
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