公开(公告)号：KR1020040021771A

公开(公告)日：2004-03-11

申请号：KR1020020053116

申请日：2002-09-04

Applicant: 삼성전자주식회사

Inventor： 김기남 ,  송윤종 ,  주흥진

IPC: H01L27/105

CPC classification number: H01L27/11502 ,  H01L27/11507

Abstract: PURPOSE: A method for manufacturing a ferroelectric memory device is provided to be capable of reducing the thickness of an upper electrode. CONSTITUTION: A lower interlayer dielectric(74) is formed on a semiconductor substrate(51). A ferroelectric capacitor(82) and a hard mask pattern are sequentially stacked on the lower interlayer dielectric. An intermetal dielectric(85a) is formed on the resultant structure and planarized to expose the hard mask pattern. By selectively etching the exposed hard mask pattern, the ferroelectric capacitor(82) is exposed. A plate line is then formed on the exposed ferroelectric capacitor.

Abstract translation: 目的：制造铁电存储器件的方法能够减小上电极的厚度。 构成：在半导体衬底（51）上形成下层间电介质（74）。 铁电电容器（82）和硬掩模图案依次层叠在下层间电介质上。 在所得结构上形成金属间电介质（85a）并平坦化以暴露硬掩模图案。 通过选择性地蚀刻暴露的硬掩模图案，暴露铁电电容器（82）。 然后在暴露的铁电电容器上形成板线。

公开(公告)号：KR100416607B1

公开(公告)日：2004-02-05

申请号：KR1020010064775

申请日：2001-10-19

Applicant: 삼성전자주식회사

Inventor： 전윤수 ,  신동원 ,  김기남

IPC: H01L27/108

CPC classification number: H01L21/76837 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  Y10S257/90

Abstract: According to embodiments of the present invention, methods of manufacturing a semiconductor device, and semiconductor devices manufactured thereby, are provided. A field region is formed that defines active regions in a semiconductor substrate. Spaced apart gates are formed on the active regions in the semiconductor substrate. The gates have sidewalls that extend away from the semiconductor substrate. First spacers are formed on the sidewalls of the gates. Second spacers are formed on the first spacers and opposite to the gates. Ion impurities are implanted into the active regions in the semiconductor substrate, adjacent to the gates, using the first and second spacers as an ion implantation mask. A portion of the second spacers is removed to widen the gaps between the gates. A dielectric layer is formed on the semiconductor substrate in the gaps between the gates.

Abstract translation: 根据本发明的实施例，提供了制造半导体器件的方法以及由此制造的半导体器件。 形成在半导体衬底中限定有源区的场区。 间隔开的栅极形成在半导体衬底中的有源区上。 栅极具有远离半导体衬底延伸的侧壁。 第一间隔物形成在门的侧壁上。 第二垫片形成在第一垫片上并与闸门相对。 使用第一和第二间隔物作为离子注入掩模，将离子杂质注入到半导体衬底中的与栅极相邻的有源区中。 部分第二间隔件被移除以扩大闸门之间的间隙。 在栅极之间的间隙中的半导体衬底上形成介电层。

公开(公告)号：KR1020030090072A

公开(公告)日：2003-11-28

申请号：KR1020020028062

申请日：2002-05-21

Applicant: 삼성전자주식회사

Inventor： 전병길 ,  김기남

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: PURPOSE: A high speed ferroelectric memory device and a writing method thereof are provided to increase an operation speed by writing '0' data with simultaneously transmitting data stored at the memory cell of a selected row. CONSTITUTION: A ferroelectric memory cell is connected to a word line and a plate line and a bit line. A plate line driver drives the above plate line. A word line decoder drives the above word line in response to a row address. A sense amplifier senses and amplifies a voltage on the above bit line. A column selection circuit connects the bit line with a data line electrically in response to a column address. A data input circuit transfers data from the external to the above data line. And a control logic controls operation timing of the plate line driver and the column selection circuit and the sense amplifier circuit and the data input circuit.

Abstract translation: 目的：提供高速铁电存储装置及其写入方法，通过同时发送存储在所选行的存储单元上的数据来写入“0”数据来提高操作速度。 构成：铁电存储单元连接到字线和板线和位线。 板线驱动器驱动上述板线。 字线解码器响应于行地址驱动上述字线。 读出放大器感测并放大上述位线上的电压。 列选择电路响应于列地址将位线与数据线电连接。 数据输入电路将数据从外部传输到上述数据线。 并且控制逻辑控制板线驱动器和列选择电路以及读出放大器电路和数据输入电路的操作定时。

公开(公告)号：KR100403629B1

公开(公告)日：2003-10-30

申请号：KR1020010029731

申请日：2001-05-29

Applicant: 삼성전자주식회사

Inventor： 양원석 ,  김기남

IPC: H01L27/108

CPC classification number: H01L21/76897

Abstract: An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of an adjacent second row. Source and drain regions are in the active regions and are arranged such that each active region comprises a drain region disposed between two source regions. A plurality of word line structures are on the substrate, arranged transverse to the rows of active regions such that that word line structures cross the active regions between the source regions and the drain regions. Respective rows of conductive pads are disposed between respective adjacent word lines structures, including first conductive pads on the source regions, second conductive pads on the drain regions, and third conductive on isolation regions separating active regions. A plurality of bit line structures are on the substrate, extending transverse to the word line structures and contacting the second conductive pads. Related methods of fabrication are also described.

Abstract translation: 集成电路器件（例如存储器件）包括衬底和在衬底中的多个有源区域行，有源区域以交错图案布置，使得第一行的有源区域与隔离的部分对准 区域分隔相邻第二行的有源区域。 源极和漏极区域在有源区域中并且被布置为使得每个有源区域包括设置在两个源极区域之间的漏极区域。 多个字线结构位于衬底上，横向于有源区的行布置，使得字线结构与源区和漏区之间的有源区交叉。 在各个相邻的字线结构之间设置各行导电焊盘，包括源极区域上的第一导电焊盘，漏极区域上的第二导电焊盘以及隔离有源区域的隔离区域上的第三导电。 多个位线结构在衬底上，横向于字线结构延伸并接触第二导电焊盘。 还描述了相关的制造方法。

公开(公告)号：KR100400033B1

公开(公告)日：2003-09-29

申请号：KR1020010006123

申请日：2001-02-08

Applicant: 삼성전자주식회사

Inventor： 양원석 ,  김기남 ,  정홍식

IPC: H01L21/28

CPC classification number: H01L23/485 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and manufacturing method thereof include a semiconductor substrate, an interlevel dielectric (ILD) layer formed on the semiconductor substrate, a first contact stud formed in the ILD layer, having a width of an entrance portion adjacent to the surface of the ILD layer larger than the width of a contacting portion adjacent to the semiconductor substrate, and a second contact stud spaced apart from the first contact stud and formed in the ILD layer. The semiconductor device further includes a landing pad formed on the ILD layer to contact the surface of the second contact stud, having a width larger than that of the second contact stud. The second contact stud has a width of a contacting portion that is the same as that of an entrance portion. Also, at least one spacer comprising an etch stopper material is formed on the sidewalls of the landing pad and the etch stopper is formed on the landing pad. The entrance portion of the first contact stud has a width about 30-60% larger than that of the contacting portion.

Abstract translation: 半导体器件及其制造方法包括半导体衬底，形成在半导体衬底上的层间介电（ILD）层，形成在ILD层中的第一接触柱，其具有与ILD层的表面相邻的入口部分的宽度 大于与半导体衬底相邻的接触部分的宽度;以及第二接触柱，与第一接触柱隔开并形成在ILD层中。 半导体器件还包括形成在ILD层上的着陆焊盘，以接触第二接触柱的表面，其宽度大于第二接触柱的宽度。 第二接触柱具有与入口部分相同的接触部分的宽度。 而且，在着陆焊盘的侧壁上形成至少一个包括蚀刻阻挡材料的隔离件，并且在着陆焊盘上形成蚀刻阻挡层。 第一接触柱的入口部分的宽度比接触部分的宽度大30-60％。

公开(公告)号：KR1020030074079A

公开(公告)日：2003-09-19

申请号：KR1020020065610

申请日：2002-10-25

Applicant: 삼성전자주식회사

Inventor： 이상우 ,  김기남 ,  송윤종

IPC: H01L27/105

Abstract: PURPOSE: A ferroelectric memory device using a via etch-stop layer and a method for manufacturing the same are provided to be capable of improving the degree of integration by improving the connection structure between a plate line and a ferroelectric capacitor. CONSTITUTION: A ferroelectric memory device is provided with a lower interlayer dielectric(20) formed on a semiconductor substrate, a plurality of ferroelectric capacitors(60) two-dimensionally arrayed along the row and column direction at the upper portion of the lower interlayer dielectric, an interlayer dielectric(70) formed at the resultant structure for exposing the upper surface of the capacitors, a via etch-stop layer pattern(80a) formed on the interlayer dielectric, an upper interlayer dielectric(95,110) formed at the upper portion of the via etch-stop layer pattern, and a plurality of plate lines(120) formed at the resultant structure for electrically connecting adjacent capacitors and contacting the via etch-stop layer pattern.

Abstract translation: 目的：提供使用通孔蚀刻停止层的铁电存储器件及其制造方法，以通过改善板极线和铁电电容器之间的连接结构来提高集成度。 构成：铁电存储器件具有形成在半导体衬底上的下层间电介质（20），在下层间电介质的上部沿列和列方向二维排列的多个强电介质电容器（60） 形成在用于暴露电容器的上表面的所得结构的层间电介质（70），形成在层间电介质上的通孔蚀刻停止层图案（80a），形成在层间电介质的上部的上层间电介质（95,110） 通过蚀刻停止层图案，以及形成在所得结构处的多个板线（120），用于电连接相邻的电容器并接触通孔蚀刻停止层图案。

公开(公告)号：KR100395766B1

公开(公告)日：2003-08-25

申请号：KR1020010006813

申请日：2001-02-12

Applicant: 삼성전자주식회사

Inventor： 김기남 ,  송윤종

IPC: H01L27/105

CPC classification number: H01L27/11502 ,  H01L21/3144 ,  H01L21/3185 ,  H01L21/76895 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60

Abstract: A ferroelectric memory device along with a method of forming the same are provided. A first interlayer insulating layer is formed on a semiconductor substrate. A buried contact structure is formed on the first interlayer insulating layer. The buried contact structure is electrically connected to the substrate through a first contact hole extending through the first interlayer insulating layer. A blocking layer covers or encapsulates the buried contact structure and the first interlayer insulating layer. A second interlayer insulating layer is formed on the blocking layer. A ferroelectric capacitor formed on the second interlayer insulating layer and is electrically connected to the buried contact structure through a second contact hole that penetrates the second interlayer insulating layer and the blocking layer.

Abstract translation: 提供了一种铁电存储器件及其形成方法。 第一层间绝缘层形成在半导体衬底上。 埋入式接触结构形成在第一层间绝缘层上。 掩埋接触结构通过延伸穿过第一层间绝缘层的第一接触孔电连接到衬底。 阻挡层覆盖或封装埋入式接触结构和第一层间绝缘层。 在阻挡层上形成第二层间绝缘层。 强电介质电容器，形成在第二层间绝缘层上，并通过贯穿第二层间绝缘层和阻挡层的第二接触孔电连接到掩埋接触结构。

公开(公告)号：KR100382719B1

公开(公告)日：2003-05-09

申请号：KR1020000049623

申请日：2000-08-25

Applicant: 삼성전자주식회사

Inventor： 정동진 ,  김기남

IPC: H01L27/105

CPC classification number: H01L28/75 ,  H01L28/55

Abstract: A semiconductor device including a ferroelectric capacitor and manufacturing method thereof are provided. The semiconductor device using a triple layered structure of metal layer/metal oxide layer/metal layer as an electrode of a capacitor is provided. According to the manufacturing method, a conductive plug electrically connected to a semiconductor substrate is formed by penetrating through a first insulating layer on the semiconductor substrate. An adhesive layer is formed on the conductive plug to form a first lower metal layer made of noble metals such as iridium that is electrically connected to the conductive plug and prevents diffusion of oxygen into the conductive plug on the first insulating layer. A conductive lower metal oxide layer is formed on the first lower metal layer, and a second lower metal layer for inducing interface lattice matching is preferably formed of platinum to form a lower electrode layer of a capacitor. A ferroelectric layer is formed of a ferroelectric material such as Pb(Zr1-xTix)O3 (PZT) on the lower electrode layer of a capacitor. A first upper metal layer for inducing interface lattice matching is formed on top of the ferroelectric layer, and a heat treatment is performed above the crystallization temperature of the ferroelectric material to induce interface lattice matching. Then, an upper metal oxide layer may be formed noble metal oxides such as iridium oxide on top of the first upper metal layer, and then a second upper metal layer for preventing diffusion of a material is formed of noble metals such as iridium on top of the upper metal oxide layer to form an upper electrode layer. A second insulating layer is formed on the upper electrode layer and the second insulating layer is patterned to form a wire therein electrically connected to the upper electrode layer.

Abstract translation: 提供了包括铁电电容器的半导体器件及其制造方法。 提供了使用金属层/金属氧化物层/金属层的三层结构作为电容器的电极的半导体器件。 根据该制造方法，通过穿透半导体衬底上的第一绝缘层来形成电连接到半导体衬底的导电插塞。 在导电插塞上形成粘合剂层以形成由贵金属（例如铱）制成的第一下金属层，所述贵金属与导电插塞电连接，并防止氧扩散到第一绝缘层上的导电插塞中。 在第一下金属层上形成导电下金属氧化物层，并且用于引起界面晶格匹配的第二下金属层优选由铂形成以形成电容器的下电极层。 铁电层由电容器的下电极层上的诸如Pb（Zr1-xTix）O3（PZT）的铁电材料形成。 在铁电层顶部形成用于引起界面晶格匹配的第一上金属层，并且在铁电材料的结晶温度以上进行热处理以引起界面晶格匹配。 然后，可以在第一上金属层上形成上金属氧化物层，形成贵金属氧化物例如氧化铱，然后在贵金属的顶部上由贵金属例如铱形成用于防止材料扩散的第二上金属层 上金属氧化物层以形成上电极层。 在上电极层上形成第二绝缘层，并且图案化第二绝缘层以在其中形成电连接到上电极层的导线。

公开(公告)号：KR100375987B1

公开(公告)日：2003-03-15

申请号：KR1020000083675

申请日：2000-12-28

Applicant: 삼성전자주식회사

Inventor： 전병길 ,  김기남

IPC: G11C29/00

CPC classification number: G11C29/785 ,  G11C29/808

Abstract: A redundancy circuit for a semiconductor memory device. The redundancy circuit includes redundancy memory cells and a redundancy word line decoder. The redundancy word line decoder has a fuse circuit that includes fuses and an output signal. The output signal is in one of three states depending on input signals. The fuse circuit controls a cutting of the fuses in accordance with the input signals so as to replace defective normal memory cells with the redundancy memory cells depending on a type of defect experienced by the defective normal memory cells.

Abstract translation: 一种用于半导体存储器件的冗余电路。 冗余电路包括冗余存储单元和冗余字线解码器。 冗余字线解码器具有包括熔丝和输出信号的熔丝电路。 根据输入信号，输出信号处于三种状态之一。 熔丝电路根据输入信号控制熔丝的切割，以便根据缺陷正常存储单元所经受的缺陷类型，用冗余存储单元替换有缺陷的正常存储单元。

公开(公告)号：KR1020030001827A

公开(公告)日：2003-01-08

申请号：KR1020010037634

申请日：2001-06-28

Applicant: 삼성전자주식회사

Inventor： 조창현 ,  조민희 ,  김기남

IPC: H01L21/8242

CPC classification number: H01L21/28176 ,  H01L21/28167 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/42368

Abstract: PURPOSE: A method for fabricating a semiconductor device having a dual gate oxide layer is provided to prevent contamination of a gate oxide layer by improving the fabricating method of the semiconductor device. CONSTITUTION: A trench oxide layer(53) is formed on a substrate(51). The first silicon oxide layer is formed on the whole surface of the substrate(51). The first conductive layer is formed on the first silicon oxide layer. The first insulating layer is formed on the first conductive layer. A gate pattern(61) and a gate oxide layer(55a) are formed by patterning the first insulating layer, the first conductive layer, and the first silicon oxide layer. The first dopant region(63) is formed on the substrate(51). A spacer(65) is formed on both sidewalls of the gate pattern(61) and the gate oxide layer(55a). The second dopant region(67) is formed on the substrate(51). A source/drain region(68) is formed by the first and the second dopant region(63,67). The second insulating layer is formed on the whole surface of the substrate(51). The third insulating layer is formed on the whole surface of the substrate(51). An interlayer dielectric is formed by planarizing the third insulating layer. An interlayer dielectric pattern(71b) having a contact hole and the second insulating layer pattern(69a) are formed by etching the interlayer dielectric and the second insulating layer. The second silicon oxide layer(79) is formed by using a thermal oxidation method.

Abstract translation: 目的：提供一种制造具有双栅氧化层的半导体器件的方法，以通过改进半导体器件的制造方法来防止栅极氧化物层的污染。 构成：在衬底（51）上形成沟槽氧化物层（53）。 第一氧化硅层形成在基板（51）的整个表面上。 第一导电层形成在第一氧化硅层上。 第一绝缘层形成在第一导电层上。 通过图案化第一绝缘层，第一导电层和第一氧化硅层来形成栅极图案（61）和栅极氧化物层（55a）。 第一掺杂剂区域（63）形成在基板（51）上。 在栅极图案（61）和栅极氧化物层（55a）的两个侧壁上形成间隔物（65）。 第二掺杂剂区域（67）形成在基板（51）上。 源极/漏极区域（68）由第一和第二掺杂剂区域（63,67）形成。 第二绝缘层形成在基板（51）的整个表面上。 第三绝缘层形成在基板（51）的整个表面上。 通过平面化第三绝缘层形成层间电介质。 通过蚀刻层间电介质和第二绝缘层形成具有接触孔和第二绝缘层图案（69a）的层间电介质图案（71b）。 通过使用热氧化法形成第二氧化硅层（79）。