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公开(公告)号：KR1019960003002B1
公开(公告)日：1996-03-02
申请号：KR1019920016976
申请日：1992-09-18
Applicant: 삼성전자주식회사
IPC: H01L27/10
Abstract: In a semiconductor memory device comprising a number of memory cell arrays, the outer contact wires are connected with together at the intersections of their rank and column by arranging the periphery region of the memory cell array in the rank or column direction of lattice structure, and the memory cells of each array are connected with together by an inner contact wire which is connected to the outer contact wire arranged in the rank direction. The operating characteristic of the semiconductor device is enhanced by reducing the resistance of the cell contact wire without increase of chip size.
Abstract translation: 在包括多个存储单元阵列的半导体存储器件中，通过将存储单元阵列的周边区域布置在格子结构的列或列方向上，外接触导线在它们的等级和列的相交处连接在一起，以及 每个阵列的存储单元通过连接到沿排列方向的外部接触导线的内部接触线连接在一起。 通过在不增加芯片尺寸的情况下降低电池接触导线的电阻来增强半导体器件的工作特性。
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公开(公告)号：KR1019940003396B1
公开(公告)日：1994-04-21
申请号：KR1019910013276
申请日：1991-07-31
Applicant: 삼성전자주식회사
IPC: G11C11/41
Abstract: The semiconductor memory device comprising a memory cell where predetermined data are stored, a first and a second bit line, a first and a second data line and a sense amplifier, characterized in that the device further comprises transporting means which could maintain potential difference of threshold voltage or two times the threshold voltage between the first and the second bit lines during first operation, prevents generation of peak current at data line or bit line.
Abstract translation: 该半导体存储器件包括存储有预定数据的存储单元，第一和第二位线，第一和第二数据线以及读出放大器，其特征在于，所述器件还包括可保持阈值的潜在差值的输送装置 在第一次操作期间在第一和第二位线之间的电压或两倍的阈值电压，防止在数据线或位线产生峰值电流。
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公开(公告)号：KR1019930006623B1
公开(公告)日：1993-07-21
申请号：KR1019900014022
申请日：1990-09-06
Applicant: 삼성전자주식회사
IPC: G11C11/407
Abstract: The data output buffer for reducing the noise caused by a variation of power supply voltage and a voltage swing comprises a pull-up control transistor (10) connected between a power supply voltage end and a driving PMOS transistor (6), a pull-down control transistor (11) connected between a driving NMOS transistor (7) and a ground voltage end, a first constant voltage unit (100) connected between the power supply voltage end and the ground voltage end, an output of which is connected to the gate of the pull-up transistor, and a second constant voltage unit (200) connected to the gate of the pull-down control transistor.
Abstract translation: 用于降低由电源电压和电压摆幅变化引起的噪声的数据输出缓冲器包括连接在电源电压端和驱动PMOS晶体管（6）之间的上拉控制晶体管（10），下拉 连接在驱动NMOS晶体管（7）和接地电压端之间的控制晶体管（11），连接在电源电压端和地电压端之间的第一恒压单元（100），其输出端连接到门 和连接到下拉控制晶体管的栅极的第二恒压单元（200）。
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公开(公告)号：KR1019930010982A
公开(公告)日：1993-06-23
申请号：KR1019910019739
申请日：1991-11-07
Applicant: 삼성전자주식회사
IPC: G11C11/40
Abstract: 본 발명은 반도체 메모리 장치의 워드라인 구동회로에 관한 것으로, 종래에 제시된 회로에서는 소정의 메모리쎌이 불량쎌로 판명되어 이를 디세이블 시키고자 상기 불량쎌의 워드라인 구동회로에 삽입되어 있는 퓨우즈 소자를 컷팅하므로서 상기 불량쎌을 비선택화하려고 하였으나 칩의 테스트나 칩을 처음으로 인에이블 시키는 등 칩에 최초로 파워－업 시킬시에 상기 워드라인 구동회로내에 있는 드라이버를 구성하는 트랜지스터의 게이트－Vcc간의 전압 상승 작용을 일으키거나 상기 드라이버내의 직류전류가 발생되는 악현상이 유발되는바, 본 발명에서는 상기 드라이버의 입력노드에 소정의 전압상승 억제용 소자인 캐패시터를 구비하므로서, 상기 메모리 쎌을 비선택화 할시에 상기 입력노드의 전압상승을 빠른 시간내에 방전시켜 상기의 전압 승을 최대한 억제하여 상기 드라이버내의 직류전류를 제거하여 대기시 전류소비를 최대한 억제하고 칩의 동작특성을 안정화시킨다.
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Patent Agency Ranking
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公开(公告)号：KR1019930005027A
公开(公告)日：1993-03-23
申请号：KR1019910014272
申请日：1991-08-19
Applicant: 삼성전자주식회사
IPC: G11C11/407
Abstract: 내용 없음.
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公开(公告)号：KR1019920010345B1
公开(公告)日：1992-11-27
申请号：KR1019900009877
申请日：1990-06-30
Applicant: 삼성전자주식회사
IPC: G11C11/40
CPC classification number: G11C7/1096 , G11C7/1078 , G11C7/22
Abstract: The write driver for improving the operation speed comprises a data input circuit (3) for buffering inverted and non-inverted input data (DIN) to data lines (DL,DLB). A pulse generator (6) detects data transitions and generates a write pulse (WN) which allows the buffered data to succeed to data lines (DL,DLB) via a transmission circuit (7). In response to the inverted write enable signal (WEB), the pulse generator (6) generates a second control pulse (WP) causing a precharge circuit (8) to charge the data lines (DL,DLB) prior to reading. Generation of the precharge pulse (WP) on the fall of the write enable signal allows a more rapid transition from write to read.
Abstract translation: 用于提高操作速度的写入驱动器包括用于将反相和非反相输入数据（DIN）缓冲到数据线（DL，DLB）的数据输入电路（3）。 脉冲发生器（6）检测数据转换并产生写入脉冲（WN），该写入脉冲允许缓冲的数据经由传输电路（7）继续到数据线（DL，DLB）。 响应于反相写入使能信号（WEB），脉冲发生器（6）产生第二控制脉冲（WP），使得预充电电路（8）在读取之前对数据线（DL，DLB）充电。 在写入使能信号的下降时产生预充电脉冲（WP）允许从写入到读取的更快速的转变。
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公开(公告)号：KR1019920006251B1
公开(公告)日：1992-08-01
申请号：KR1019890015443
申请日：1989-10-26
Applicant: 삼성전자주식회사
Inventor： 박용보
CPC classification number: H03K19/018521 , H03K19/01721
Abstract: The level converter for converting a TTL level of input signal to a CMOS level comprises a NOR gate circuit (1), including a first voltage pull-up PMOS transistor (PI2), to which the TTL signal is inputted, an inverter (INV) connected to the NOR gate circuit, and a speed control circuit (2). The NOR gate circuit has a PMOS (PI1) and an NMOS (NI1) controlled by a control signal (CS), as well as a CMOS transistor (PI2, NI2) fed by the TTL signal. The speed control circuit includes a second voltage pull-up PMOS transistor (PI4). The two transistors (PI2,PI4) are connected in parallel between VCC and the input to the inverter. A fast conversion speed is obtained by turning on both PMOS (PI2,PI4) when the TTL signal goes from the high level to the low level.
Abstract translation: 用于将输入信号的TTL电平转换为CMOS电平的电平转换器包括NOR门电路（1），其包括输入TTL信号的第一电压上拉PMOS晶体管（PI2），反相器（INV） 连接到或非门电路，以及速度控制电路（2）。 NOR门电路具有由控制信号（CS）控制的PMOS（PI1）和NMOS（NI1）以及由TTL信号馈送的CMOS晶体管（PI2，NI2）。 速度控制电路包括第二电压上拉PMOS晶体管（PI4）。 两个晶体管（PI2，PI4）在VCC和反相器的输入端并联连接。 当TTL信号从高电平变为低电平时，通过接通PMOS（PI2，PI4）获得快速转换速度。
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