公开(公告)号：KR1020110135693A

公开(公告)日：2011-12-19

申请号：KR1020100055561

申请日：2010-06-11

Applicant: 삼성전자주식회사

Inventor： 박찬 ,  강창석 ,  장성일 ,  최병인

IPC: G11C16/34 ,  G11C16/28 ,  G11C16/30

CPC classification number: G11C16/10 ,  G11C16/3418 ,  G11C16/34 ,  G11C16/28 ,  G11C16/30

Abstract: PURPOSE: A nonvolatile memory device including a dummy memory cell and a programming method thereof are provided to improve the reliability of a nonvolatile memory device by preventing disturbance due to a hot carrier. CONSTITUTION: A program voltage and a disturbance preventing voltage are generated(S110). It is determined whether a distance between the selected word line and a dummy word line is longer than a reference distance(S120). If the distance between the selected word line and the dummy word line is longer than the reference distance, the program voltage is provided to the selected word line and the disturbance preventing voltage is provided to the dummy word line(S130). If the distance between the selected word line and the dummy word line is shorter than the reference distance, the program voltage is provided to the selected word line and the disturbance preventing voltage is provided to the dummy word line(S140).

Abstract translation: 目的：提供包括虚拟存储单元及其编程方法的非易失性存储器件，以通过防止由热载体引起的干扰来提高非易失性存储器件的可靠性。 构成：产生编程电压和防干扰电压（S110）。 确定所选字线和虚拟字线之间的距离是否长于参考距离（S120）。 如果所选字线和虚拟字线之间的距离长于参考距离，则将编程电压提供给所选字线，并将防干扰电压提供给虚拟字线（S130）。 如果所选字线和虚拟字线之间的距离比参考距离短，则将编程电压提供给所选择的字线，并将防干扰电压提供给虚拟字线（S140）。

公开(公告)号：KR100885918B1

公开(公告)日：2009-02-26

申请号：KR1020070038326

申请日：2007-04-19

Applicant: 삼성전자주식회사

Inventor： 박진우 ,  조차제 ,  안은철 ,  황태주 ,  유혜정 ,  박찬

IPC: H01L23/12

CPC classification number: H01L24/73 ,  H01L24/12 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/06134 ,  H01L2224/06136 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83194 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: 반도체 디바이스 스택 패키지(semiconductor device stack package structure)에 있어 복수의 반도체 칩(chip)의 활성면이 기판(substrate)을 향하고, 복수의 반도체 칩 사이의 공간을 이용하여 상부 칩이 기판(substrate)에 범프(bump)로 연결되어 구현되는 패키지, 이를 이용한 전기장치 및 그 패키지의 제조방법에 관해 개시한다. 본 발명은 와이어루프(wire loop)가 없기 때문에 와이어루프(wire loop)로 인한 높이 증가가 없고, 전기적 통로(electrical path)의 길이를 줄여 전기적 성능(electrical performance) 특성을 향상시킨다. 이를 위하여 본 발명은 플립 칩(flip chip)만으로 이루어진 구조로서 복수의 칩으로 적층되며 다양한 스택 패키지 응용이 가능한 장점이 있다.
플립 칩(flip chip), 스택(stack), 페이스다운(face down), 범프(bump)

Abstract translation: 在半导体器件堆叠封装及其形成方法中，封装包括：衬底; 堆叠在所述基板上并具有朝向所述基板的方向取向的有源面的多个下部芯片; 以及设置在下芯片上的至少一个上芯片，并且经由设置在下芯片之间的凸块连接到基板。 由于没有形成线环，堆叠封装的高度不会增加，并且电气路径被缩短，从而提高了堆叠封装的电性能。 此外，半导体器件堆叠封装具有倒装芯片结构，因此可以以各种方式堆叠多个半导体芯片。

公开(公告)号：KR1020080094203A

公开(公告)日：2008-10-23

申请号：KR1020070038326

申请日：2007-04-19

Applicant: 삼성전자주식회사

Inventor： 박진우 ,  조차제 ,  안은철 ,  황태주 ,  유혜정 ,  박찬

IPC: H01L23/12

CPC classification number: H01L24/73 ,  H01L24/12 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/06134 ,  H01L2224/06136 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83194 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device stack package is provided to remove a height increase caused by a wire loop by eliminating the necessity of the entire loop. A plurality of lower chips(130) are stacked on a substrate(100) wherein the active surface of the lower chip faces the substrate. At least one upper chip is disposed on the lower chip, electrically connected to the substrate through a bump positioned among the plurality of lower chips. The lower chip can be electrically connected to the substrate through a bump positioned between the lower chip and the substrate. Solder balls(110) can be included on the lower surface of the substrate.

Abstract translation: 提供半导体器件堆叠封装以通过消除整个环路的必要性来消除由线环引起的高度增加。 多个下部芯片（130）堆叠在基板（100）上，其中下部芯片的有源表面面向基板。 至少一个上芯片设置在下芯片上，通过位于多个下芯片之间的凸块与基板电连接。 下芯片可以通过位于下芯片和衬底之间的凸块电连接到衬底。 焊球（110）可以包括在基板的下表面上。

公开(公告)号：KR100830587B1

公开(公告)日：2008-05-21

申请号：KR1020070002978

申请日：2007-01-10

Applicant: 삼성전자주식회사

Inventor： 홍종욱 ,  박찬 ,  정상일

IPC: H04N5/369

CPC classification number: H04N9/045 ,  H04N5/35563

Abstract: An image sensor and an image display method using the same are provided to recognize an object in an image clearly even if the image is photographed at high luminous intensity. An image sensor comprises main pixels, each of which has sub color pixels and a compensation pixel, wherein the dynamic range of the compensation pixel is larger than that of the sub color pixel. The image sensor, viewed in the vertical structure, comprises a substrate(110), light receiving elements(120), interlayer insulating layers(130), wires(140), color filters(150), and micro lenses(170). The substrate includes a first and a second pixel area. The color filters are placed to correspond to the light receiving elements on the interlayer insulating layers. Some of the wires are extended to the light receiving elements in the second pixel area so that a light receiving area of the second pixel area is smaller than that of the first pixel area. The first pixel area includes red, green, and blue pixel areas(RA,GA,BA).

Abstract translation: 提供图像传感器和使用其的图像显示方法，即使以高发光强度拍摄图像，也能清楚地识别图像中的对象。 图像传感器包括主像素，每个像素具有子颜色像素和补偿像素，其中补偿像素的动态范围大于子像素的动态范围。 在垂直结构中观看的图像传感器包括基板（110），光接收元件（120），层间绝缘层（130），导线（140），滤色器（150）和微透镜（170）。 衬底包括第一和第二像素区域。 放置滤色器以对应于层间绝缘层上的光接收元件。 一些电线延伸到第二像素区域中的光接收元件，使得第二像素区域的光接收区域小于第一像素区域的光接收区域。 第一像素区域包括红色，绿色和蓝色像素区域（RA，GA，BA）。