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公开(公告)号：KR101652386B1
公开(公告)日：2016-09-12
申请号：KR1020090093968
申请日：2009-10-01
Applicant: 삼성전자주식회사
IPC: H01L23/00 , H01L23/498
CPC classification number: H01L24/06 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/13 , H01L2224/02125 , H01L2224/03464 , H01L2224/0401 , H01L2224/05011 , H01L2224/05018 , H01L2224/05124 , H01L2224/05147 , H01L2224/05556 , H01L2224/05558 , H01L2224/05569 , H01L2224/05572 , H01L2224/05655 , H01L2224/06051 , H01L2224/13018 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2224/13116 , H01L2224/1403 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/00013 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15788 , H01L2924/181 , H01L2924/19041 , H01L2924/00014 , H01L2924/0105 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552 , H01L2924/00 , H01L2924/00012
Abstract: 범프구조물을갖는집적회로칩에있어서, 다수의도전성구조물및 배선라인을구비하는집적회로구조물의패드영역및 의사패드영역의각각에제1 및제2 패드전극이배치된다. 제1 전극패드의상면을노출하는제1 개구및 배선라인으로부터이격된제2 전극패드의주변부를노출하는적어도하나의제2 개구를구비하는보호막패턴이집적회로구조물의상면에배치된다. 제1 개구를통하여제1 전극패턴과전기적으로접속하는제1 범프구조물및 제2 개구를통하여제2 전극패턴과전기적으로접속하는제2 범프구조물이상기보호막패턴상에배치된다. 상기제2 범프구조물의하부에배치된배선라인에대한응력집중을방지할수 있다.
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公开(公告)号：KR1020150043135A
公开(公告)日：2015-04-22
申请号：KR1020130122194
申请日：2013-10-14
Applicant: 삼성전자주식회사
CPC classification number: H05K3/24 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73204 , H01L2224/73265 , H01L2924/18161 , H05K2201/10674 , H05K2203/049 , H01L2924/00014 , H01L2924/00
Abstract: 본발명의사상은 PCB 내부배선부를금속막으로덮음으로써, PCB에형성되는배선부의산화및 오염을방지하면서도, PCB 및패키지의신뢰성을향상시킬수 있는금속막을포함한인쇄회로기판(PCB) 및그것을포함한반도체패키지를제공한다. 인쇄회로기판은하면및 상면을구비한평판구조의절연층; 상기절연층의상기상면및 하면중 적어도한쪽면으로형성되고, 다수의배선패턴을구비한배선부; 및상기다수의배선패턴을구비한배선부를덮는금속막을포함한다. 또한, 상기반도체패키지는다수의배선패턴을구비한배선부를덮는금속막을포함하는인쇄회로기판; 상기인쇄회로기판상면및 하면중 적어도한 면에와이어본딩또는플립-칩(flip-chip) 본딩으로실장되는반도체칩; 및상기인쇄회로기판의상면및 하면중 적어도한 면을덮으면서형성되는몰딩부재를포함한다.
Abstract translation: 本发明的思想提供了一种印刷电路板（PCB），其包括金属层和包含该印刷电路板的半导体封装，能够提高封装和PCB的可靠性并防止PCB上形成的布线部件被氧化， 被金属层覆盖PCB上的接线部分污染。 PCB包括：具有平面结构的绝缘层，其包括底侧和顶侧，所述布线部至少形成在绝缘层的顶侧或底侧并且包括多个布线图案，并且 覆盖配线部的配线图案的金属层。 此外，半导体封装包括PCB，其包括用布线图案覆盖布线部分的金属层，半导体芯片至少安装在PCB的顶侧或底侧，具有布线接合或触发器， 芯片接合，以及覆盖PCB的顶侧或底侧的成型构件。
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公开(公告)号：KR1020110036354A
公开(公告)日：2011-04-07
申请号：KR1020090093968
申请日：2009-10-01
Applicant: 삼성전자주식회사
IPC: H01L23/00 , H01L23/498
CPC classification number: H01L24/06 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/13 , H01L2224/02125 , H01L2224/03464 , H01L2224/0401 , H01L2224/05011 , H01L2224/05018 , H01L2224/05124 , H01L2224/05147 , H01L2224/05556 , H01L2224/05558 , H01L2224/05569 , H01L2224/05572 , H01L2224/05655 , H01L2224/06051 , H01L2224/13018 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2224/13116 , H01L2224/1403 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/00013 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15788 , H01L2924/181 , H01L2924/19041 , H01L2924/00014 , H01L2924/0105 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552 , H01L2924/00 , H01L2924/00012
Abstract: PURPOSE: An integrated circuit chip, integrated circuit chip manufacturing method, flip chip package with the integrated circuit chip and flip chip package manufacturing method are provided to separate a second bump structure from the central line of a wiring line as much as a fixed distance, thereby preventing stress from being concentrated on the wiring line. CONSTITUTION: An integrated circuit structure comprises a first area with a wiring line and a second area without a wiring line. The integrated circuit structure comprises a plurality of conductive structures and a wiring line(116). An electrode pad comprises a first electrode pad and a second electrode pad(114b). A passivation layer pattern comprises a first opening and a second opening and is arranged on the electrode pad. A bump structure comprises a first bump structure and a second bump structure(130).
Abstract translation: 目的：提供集成电路芯片，集成电路芯片制造方法，具有集成电路芯片和倒装芯片封装制造方法的倒装芯片封装，以将多个第二凸块结构与布线的中心线分开多达固定距离， 从而防止应力集中在布线上。 构成：集成电路结构包括具有布线的第一区域和没有布线的第二区域。 集成电路结构包括多个导电结构和布线（116）。 电极焊盘包括第一电极焊盘和第二电极焊盘（114b）。 钝化层图案包括第一开口和第二开口，并且布置在电极焊盘上。 凸块结构包括第一凸块结构和第二凸块结构（130）。
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公开(公告)号：KR1020100097845A
公开(公告)日：2010-09-06
申请号：KR1020090016699
申请日：2009-02-27
Applicant: 삼성전자주식회사
IPC: H01L23/488 , H01L21/60
CPC classification number: H01L2224/16 , H01L2924/01046 , H01L2924/01078 , H01L2924/15311 , H01L24/10 , H01L23/49816 , H01L23/522 , H01L2224/03914 , H01L2224/1133
Abstract: PURPOSE: A bump structure and a semiconductor package having the same are provided to offer an opening with an optimized aspect ratio which guarantees the electrical reliability between a bump and a pad. CONSTITUTION: An insulating layer(120) is formed on the upper side of a semiconductor chip(110). A semiconductor chip comprises a pad(112). An opening(128) comprises an opening which exposes the pad. The ratio of the height(H) and the width(D) of the opening is 0.5:1, respectively. The insulating layer comprises a silicon oxide film(122), a silicon nitride film(124), and a dielectric layer(126).
Abstract translation: 目的：提供一种凸块结构和具有该凸块结构的半导体封装以提供具有优化的纵横比的开口，其保证凸块和垫之间的电可靠性。 构成：在半导体芯片（110）的上侧形成有绝缘层（120）。 半导体芯片包括焊盘（112）。 开口（128）包括露出垫的开口。 开口的高度（H）和宽度（D）的比率分别为0.5：1。 绝缘层包括氧化硅膜（122），氮化硅膜（124）和电介质层（126）。
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Patent Agency Ranking
公开(公告)号：KR1020100087564A
公开(公告)日：2010-08-05
申请号：KR1020090006655
申请日：2009-01-28
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L24/11 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/05026 , H01L2224/05124 , H01L2224/05571 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05672 , H01L2224/05684 , H01L2224/10126 , H01L2224/11334 , H01L2224/11462 , H01L2224/11464 , H01L2224/11472 , H01L2224/11849 , H01L2224/11901 , H01L2224/13006 , H01L2224/13014 , H01L2224/13076 , H01L2224/13099 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/3512 , H01L2924/00014 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2924/00012 , H01L2224/05552
Abstract: PURPOSE: A method for forming a connection terminal including a solder unit and a solder unit supporter is provided to efficiently reduce an external impact by changing the propagation direction of a crack. CONSTITUTION: A substrate with a UBM(Under Bump Metallurgy)(116) is prepared. A solder unit(141) comprised of a lower side of a cylindrical shape and an upper side of a sphere shape is formed. The lower side is combined with the UBM. A solder unit supporter(130) is formed on the substrate and surrounds the lower side. The solder unit supporter is arranged on the UBM.
Abstract translation: 目的：提供一种用于形成包括焊料单元和焊料单元支撑件的连接端子的方法，以通过改变裂纹的传播方向来有效地减少外部冲击。 构成：制备了具有UBM（Under Bump Metallurgy）（116）的底物。 形成由圆柱形的下侧和球形的上侧构成的焊接单元（141）。 下侧与UBM组合。 焊料单元支撑件（130）形成在基板上并且围绕下侧。 焊接单元支架安装在UBM上。
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公开(公告)号：KR100876083B1
公开(公告)日：2008-12-26
申请号：KR1020070059595
申请日：2007-06-18
Applicant: 삼성전자주식회사
IPC: H01L23/48
CPC classification number: H01L2224/73104
Abstract: A semiconductor package including a semiconductor chip package is provided to improve the electric reliability of a semiconductor chip package by including a molding layer having a meniscus concave. A semiconductor chip package comprises a semiconductor chip(110), a solder ball(112) for a bump and a molding layer(120). The semiconductor chip includes a side including bonding pads, a second side facing the first side and a side. The solder ball for a bump is provided on bonding pads. The molding layer is provided so that each part of the solder balls for bump is exposed with covering the first side. The molding layer between the adjacent solder balls for bumps has a meniscus concave. The solder balls for bump comprise a cross section having a maximum diameter parallel to the first side. Height from the first side to the edge contacting with the solder ball for the bump of the meniscus concave is within 1/7 length of the maximum diameter of the solder ball to a lower part or upper part.
Abstract translation: 提供包括半导体芯片封装的半导体封装，以通过包括具有弯月面凹入的模制层来提高半导体芯片封装的电可靠性。 半导体芯片封装包括半导体芯片（110），用于凸块的焊球（112）和模制层（120）。 半导体芯片包括具有接合焊盘的一侧，面对第一侧和第二侧的第二侧。 在焊盘上提供用于凸块的焊球。 提供模制层，使得用于凸块的焊球的每个部分以覆盖第一侧的方式暴露。 用于凸块的相邻焊球之间的模制层具有弯月形凹面。 用于凸块的焊球包括具有平行于第一侧的最大直径的横截面。 从弯月形凹坑的凸块接触焊球的第一侧到边缘的高度在焊球的最大直径到下半部或上半部分的长度的1/7以内。
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公开(公告)号：KR1020080110172A
公开(公告)日：2008-12-18
申请号：KR1020070058583
申请日：2007-06-14
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L2224/04105 , H01L2224/12105 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2924/15311 , H01L2924/15313 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L25/074 , H01L21/268 , H01L23/28 , H01L23/481 , H01L23/53209
Abstract: A PIP package including via hole and a manufacturing method thereof is provided to improve mechanical strength and facilitate manufacturing. A PIP(package-in-package) package(100) comprises a first package(110), a second package(120), passivation layers(117, 127), metal wiring(105). The first package comprises a first die(111). The second package comprises a second die(121). The second package is laminated on the first package with being reversed. The passivation layer comprises the via hole(103). The passivation layer contains the first package and the second package. The via hole electrically connects the first package and the second package. The metal wiring electrically connects the first package and the second package through the via hole.
Abstract translation: 提供包括通孔的PIP封装及其制造方法以提高机械强度并促进制造。 PIP（封装封装）封装（100）包括第一封装（110），第二封装（120），钝化层（117,127），金属布线（105）。 第一包装包括第一管芯（111）。 第二包装包括第二管芯（121）。 将第二包装层叠在第一包装上并被反向。 钝化层包括通孔（103）。 钝化层包含第一封装和第二封装。 通孔电连接第一封装和第二封装。 金属布线通过通孔将第一封装和第二封装电连接。
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公开(公告)号：KR1020080101070A
公开(公告)日：2008-11-21
申请号：KR1020070047293
申请日：2007-05-15
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L24/85 , H01L23/5389 , H01L24/24 , H01L24/48 , H01L24/73 , H01L24/82 , H01L24/83 , H01L24/91 , H01L25/0657 , H01L2224/05553 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73227 , H01L2224/73265 , H01L2224/83 , H01L2224/85 , H01L2224/92 , H01L2224/92244 , H01L2224/92247 , H01L2225/0651 , H01L2225/06524 , H01L2225/06527 , H01L2225/06582 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/10161 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/78 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
Abstract: The semiconductor package having various sizes of chips by using the chip insertion type interface board is provided. The chip insertion type interface board(50) comprises; the chip having a plurality of chip pads(39); the substrate(31) having a plurality of rewiring pads(33) for rewiring chip pads having the chip; the bonding wire(41) connecting the chip pad and rewiring pad; the protective layer(43) having the via hole(45) which exposes the rewiring pad while burying the chip and the substrate; the via(47) connected with the rewiring pad through the via hole.
Abstract translation: 提供了通过使用芯片插入型接口板具有各种尺寸的芯片的半导体封装。 芯片插入型接口板（50）包括： 所述芯片具有多个芯片焊盘（39）; 所述基板（31）具有多个重新布线焊盘（33），用于重新布线具有所述芯片的芯片焊盘; 连接芯片焊盘和重新布线焊盘的接合线（41） 所述保护层（43）具有通孔（45），所述通孔（45）在掩埋所述芯片和所述基板的同时露出所述再布线板; 所述通孔（47）通过所述通孔与所述重新接线焊盘连接。
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公开(公告)号：KR1020080046827A
公开(公告)日：2008-05-28
申请号：KR1020060116328
申请日：2006-11-23
Applicant: 삼성전자주식회사
CPC classification number: H05K1/02 , H01L23/498 , H01L24/02 , H01L24/03 , H01L24/11 , H01L2224/03 , H01L2224/0401 , H01L2224/11009 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H05K1/09 , H05K3/0052 , H05K3/243 , H05K3/4007 , H05K2201/0391 , H05K2201/09781 , H05K2203/0315 , H05K2203/175
Abstract: A method of fabricating an electronic device having a sacrificial anode, and an electronic device fabricated by the same are provided to suppress corrosion of a metal interconnection by forming a sacrificial pattern electrically connected to the metal interconnection, thereby preventing deterioration of electrical properties of the electrical device. A method of fabricating an electronic device comprises the steps of: preparing a substrate(1) having a first area(C) and a second area(S); forming a metal interconnection(5) extending from the first area to the second area on the substrate; forming an insulating layer(10) on the substrate; forming a sacrificial pattern(15) electrically connected to the metal interconnection, wherein the sacrificial pattern is formed on the second area to act as a sacrificial anode of cathodic projection for preventing corrosion of the metal interconnection; and patterning the insulating layer to form an opening(10b) which exposes the metal interconnection on the first area.
Abstract translation: 提供一种制造具有牺牲阳极的电子器件的方法和由其制造的电子器件，以通过形成与金属互连电连接的牺牲图案来抑制金属互连的腐蚀，从而防止电气性能的劣化 设备。 一种制造电子器件的方法包括以下步骤：制备具有第一区域（C）和第二区域（S）的衬底（1）; 形成从所述第一区域延伸到所述基板上的所述第二区域的金属互连（5）; 在所述基板上形成绝缘层（10）; 形成电连接到所述金属互连的牺牲图案（15），其中所述牺牲图案形成在所述第二区域上，以用作阴极突起的牺牲阳极，以防止金属互连的腐蚀; 以及图案化所述绝缘层以形成在所述第一区域上暴露所述金属互连的开口（10b）。
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