公开(公告)号：KR1020080105612A

公开(公告)日：2008-12-04

申请号：KR1020070053408

申请日：2007-05-31

Applicant: 삼성전자주식회사

Inventor： 변경래 ,  조홍

IPC: G11C11/15

CPC classification number: G11C11/161 ,  H01L27/222 ,  H01L43/08

Abstract: A magnetic memory device and method of forming the same is provided to improve the reliability of the device since a free layer and insulating layer of the magnetic tunnel junction are not damaged by an etch stopper layer. In a magnetic memory device, a pinning layer(142) is laminated on a semiconductor substrate and a pinned layer(144) and an insulating layer(146). A free layer(148) is on the insulating layer, and a liner oxidation(160) is on the free layer. An upper electrode(150) is arranged in the liner oxidation and contacts the free layer, and an etch stopper layer(170) is arranged on the liner oxidation. An interlayer insulating layer is arranged on the etch stopper layer.

Abstract translation: 提供一种磁存储器件及其形成方法以提高器件的可靠性，因为磁性隧道结的自由层和绝缘层不被蚀刻阻挡层损坏。 在磁存储器件中，钉扎层（142）层压在半导体衬底和钉扎层（144）和绝缘层（146）上。 自由层（148）位于绝缘层上，衬里氧化（160）位于自由层上。 上部电极（150）布置在衬里氧化中并与自由层接触，并且在衬里氧化上布置有蚀刻停止层（170）。 在蚀刻阻挡层上设置层间绝缘层。

公开(公告)号：KR100843145B1

公开(公告)日：2008-07-02

申请号：KR1020060123086

申请日：2006-12-06

Applicant: 삼성전자주식회사

Inventor： 이선우 ,  변경래 ,  이준영 ,  김중현 ,  최영문 ,  윤홍식

IPC: H01L21/20 ,  B82Y40/00

Abstract: 반도체 집적 회로 장치의 제조 방법이 제공된다. 반도체 집적 회로 장치의 제조 방법은 반도체 기판 상에 하부 배선, 촉매층 및 버퍼층을 차례로 형성하고, 버퍼층을 덮도록 층간 절연막을 형성하고, 층간 절연막을 관통하여 버퍼층의 일부 상면이 노출되도록 콘택홀을 형성하고, 콘택홀에 의해 노출된 버퍼층을 제거하여, 촉매층을 노출시키고, 콘택홀에 의해 노출된 촉매층에서부터 탄소 나노 튜브를 성장시켜 콘택홀을 매립하는 것을 포함한다.
반도체 집적 회로 장치, 탄소 나노 튜브

公开(公告)号：KR1020080032518A

公开(公告)日：2008-04-15

申请号：KR1020060098460

申请日：2006-10-10

Applicant: 삼성전자주식회사

Inventor： 최영문 ,  여인석 ,  이선우 ,  윤홍식 ,  변경래

IPC: H01L21/28 ,  H01L21/3205 ,  B82Y40/00

CPC classification number: H01L21/76843 ,  B82Y40/00 ,  H01L21/02527 ,  H01L21/02532 ,  H01L21/02606 ,  H01L21/76871 ,  H01L21/76877

Abstract: A contact structure and a method of forming the same are provided to increase the density of a nano tube within a contact hole, and to enable formation of the nano tube although diameter of the contact hole decreases by entirely filling nano materials within the contact hole, thereby preventing contact defects of a highly integrated device. A method for forming a contact structure comprises the steps of: forming a lower electrode(10) on a substrate(1); forming an interlayer insulation film(15) having a contact hole(25) on the substrate having the lower electrode; successively forming a barrier layer and a catalyst layer on the substrate having the contact hole; forming a photoresist film filling the contact hole on the substrate which has the barrier layer and the catalyst layer; etching back the photoresist film to expose the catalyst layer formed on the interlayer insulation film, as remaining the photoresist film within the contact hole; etching back the catalyst layer and the barrier layer by using etching gas containing chlorine gas, to form a barrier layer pattern(27') and a catalyst layer pattern(30') remaining within the contact hole; removing the residual photoresist film in the contact hole through an ashing process; and forming nano materials filling inside the contact hole by using the catalyst layer pattern as a seed layer.

Abstract translation: 提供接触结构及其形成方法以增加接触孔内的纳米管的密度，并且能够形成纳米管，尽管通过在接触孔内完全填充纳米材料而使接触孔的直径减小， 从而防止高度集成的装置的接触缺陷。 形成接触结构的方法包括以下步骤：在基底（1）上形成下电极（10）; 在具有下电极的基板上形成具有接触孔（25）的层间绝缘膜（15） 在具有接触孔的基板上依次形成阻挡层和催化剂层; 形成填充具有阻挡层和催化剂层的基板上的接触孔的光致抗蚀剂膜; 蚀刻光致抗蚀剂膜以暴露形成在层间绝缘膜上的催化剂层，将光致抗蚀剂膜保留在接触孔内; 通过使用包含氯气的蚀刻气体来回蚀催化剂层和阻挡层，以形成保留在接触孔内的阻挡层图案（27'）和催化剂层图案（30'）; 通过灰化处理去除接触孔中残留的光致抗蚀剂膜; 通过使用催化剂层图案作为种子层，形成填充在接触孔内的纳米材料。

公开(公告)号：KR100791948B1

公开(公告)日：2008-01-04

申请号：KR1020060093844

申请日：2006-09-27

Applicant: 삼성전자주식회사

Inventor： 이선우 ,  여인석 ,  이준영 ,  김중현 ,  윤홍식 ,  변경래

IPC: H01L21/28 ,  H01L21/3205 ,  B82Y40/00

CPC classification number: H01L21/76814 ,  H01L21/76823 ,  H01L21/76829 ,  H01L21/76876 ,  H01L21/76879 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/1683 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a carbon nano-tube interconnection is provided to form a carbon nano-tube interconnection without causing an interface rupture phenomenon by growing a carbon nano tube only on a catalyst metal pattern. A metal oxide is formed on a substrate(100). An insulation layer pattern(120) is formed on the metal oxide layer, including an opening exposing the surface of the metal oxide layer. The metal oxide layer exposed to the opening is transformed into a catalyst metal layer pattern(113). A carbon nano tube is grown from the catalyst metal layer pattern to form a carbon nano-tube interconnection(130) in the opening. The metal oxide layer can be formed by oxidizing the metal layer in an atmosphere in which oxygen-including oxide gas is supplied after the metal layer is formed on the substrate.

Abstract translation: 提供形成碳纳米管互连的方法以形成碳纳米管互连，而不会通过仅在催化剂金属图案上生长碳纳米管而引起界面破裂现象。 在基板（100）上形成金属氧化物。 在金属氧化物层上形成绝缘层图案（120），其包括露出金属氧化物层的表面的开口。 暴露于开口的金属氧化物层转变为催化剂金属层图案（113）。 从催化剂金属层图案生长碳纳米管，以在开口中形成碳纳米管互连（130）。 金属氧化物层可以通过在形成金属层之后在供给含氧氧化物气体的气氛中氧化金属层而形成。

公开(公告)号：KR100660539B1

公开(公告)日：2006-12-22

申请号：KR1020040059812

申请日：2004-07-29

Applicant: 삼성전자주식회사

Inventor： 변경래 ,  조성래

IPC: G11C11/15

CPC classification number: H01L43/12 ,  G11C11/16 ,  H01L27/228 ,  H01L43/08 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49052 ,  Y10T29/49155

Abstract: 자기 기억 소자 및 그 형성 방법을 제공한다. 이 소자는 기판 상에 형성된 하부 절연막 상에 배치된 디지트 라인, 및 중간 절연막을 개재하여 디지트 라인 상에 배치된 자기 터널 접합 유닛을 포함한다. 상부 절연막을 개재하여 자기 터널 접합 유닛 상에 비트 라인이 배치된다. 비트 라인은 디지트 라인을 가로지른다. 자기 집속부는 디지트 라인 및 비트 라인 중에 선택된 적어도 하나의 양측벽에 형성된 스페이서를 포함한다. 상기 집속부는 강자성체로 이루어진다.

公开(公告)号：KR1020060127507A

公开(公告)日：2006-12-13

申请号：KR1020050048531

申请日：2005-06-07

Applicant: 삼성전자주식회사

Inventor： 고화영 ,  주석호 ,  배병재 ,  김희석 ,  변경래 ,  함진환

IPC: H01L27/105

CPC classification number: H01L28/55 ,  H01L21/32139 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65

Abstract: A method for manufacturing a ferroelectric capacitor and a semiconductor device manufacturing method using the same are provided to improve an effective surface of the capacitor by using a hard mask structure composed of first and second hard masks. A lower electrode structure(130) composed of at least one or more lower electrode layers is formed on a substrate(100). A ferroelectric film(135) is formed on the lower electrode structure. An upper electrode layer(140) is formed on the ferroelectric film. A hard mask structure(165) composed of first and second hard masks is formed on the upper electrode layer. A ferroelectric capacitor is completed on the resultant structure by an etching process using the hard mask structure as an etch mask.

Abstract translation: 提供一种强电介质电容器的制造方法和使用该方法的半导体器件制造方法，通过使用由第一和第二硬掩模构成的硬掩模结构来改善电容器的有效表面。 在基板（100）上形成由至少一个或多个下电极层构成的下电极结构（130）。 铁电薄膜（135）形成在下电极结构上。 在强电介质膜上形成上电极层（140）。 在上电极层上形成由第一和第二硬掩模构成的硬掩模结构（165）。 通过使用硬掩模结构作为蚀刻掩模的蚀刻工艺，在所得结构上完成铁电电容器。