모뎀 데이터에 따라 코어 스위칭이 수행되는 애플리케이션 프로세서 및 이를 포함하는 시스템 온 칩
    23.
    发明公开
    모뎀 데이터에 따라 코어 스위칭이 수행되는 애플리케이션 프로세서 및 이를 포함하는 시스템 온 칩 审中-实审
    其中根据调制解调器数据执行核心切换的应用处理器和片上系统

    公开(公告)号:KR1020170106774A

    公开(公告)日:2017-09-22

    申请号:KR1020160030317

    申请日:2016-03-14

    CPC classification number: H04W52/0229 H04W52/028 Y02D70/1262 Y02D70/168

    Abstract: 모뎀데이터에따라코어스위칭이수행되는애플리케이션프로세서및 이를포함하는시스템온 칩이제공된다. 애플리케이션프로세서는, 단위시간당 제1 데이터를처리하는제1 코어, 단위시간당 제1 데이터보다많은제2 데이터를처리하는제2 코어, 및커뮤니케이션프로세서에수신되는메시지신호의분석결과와센싱신호를고려하거나, 또는커뮤니케이션프로세서에제공되는전력을고려하여제1 코어와제2 코어중 어느하나의활성화(active) 여부를결정하는룩업테이블을포함한다.

    Abstract translation: 提供了根据调制解调器数据执行核心切换的应用处理器和包括应用处理器的片上系统。 应用处理器包括每单位时间处理第一数据的第一核,每单位时间处理比第一数据多的数据的第二核,以及考虑通信处理器接收的消息信号的分析结果和感测信号的第二处理器 或者考虑提供给通信处理器的功率确定第一核心和第二核心中的任何核心是否活动的查找表。

    어플리케이션 프로세서, 이를 구비하는 모바일 기기 및 어플리케이션 프로세서를 위한 클럭 신호 선택 방법
    24.
    发明公开
    어플리케이션 프로세서, 이를 구비하는 모바일 기기 및 어플리케이션 프로세서를 위한 클럭 신호 선택 방법 审中-实审
    应用处理器,具有该处理器的移动设备以及选择用于应用处理器的时钟信号的方法

    公开(公告)号:KR1020140050290A

    公开(公告)日:2014-04-29

    申请号:KR1020120116507

    申请日:2012-10-19

    Inventor: 주영표 신택균

    Abstract: An application processor includes: a main central processing unit which operates based on an external main clock signal received from one or more external clock sources in an active mode; one or more internal clock sources which generate internal clock signals; and a sensor sub-system which performs a processing operation regarding the sensing data received in a predetermined period from one or more sensor modules in an active mode or a sleep mode, and operates based on an internal clock signal or an external sub-clock signal received from an external clock source depending to the operation speed required for the sensing data processing operation.

    Abstract translation: 应用处理器包括:主中央处理单元,其基于在活动模式中从一个或多个外部时钟源接收的外部主时钟信号进行操作; 产生内部时钟信号的一个或多个内部时钟源; 以及传感器子系统,其以在活动模式或休眠模式中的一个或多个传感器模块执行关于在预定时段内接收的感测数据的处理操作,并且基于内部时钟信号或外部子时钟信号 根据感测数据处理操作所需的操作速度从外部时钟源接收。

    동적 전압 주파수 스케일링 방법, 어플리케이션 프로세서 및 이를 구비하는 모바일 기기
    25.
    发明公开
    동적 전압 주파수 스케일링 방법, 어플리케이션 프로세서 및 이를 구비하는 모바일 기기 审中-实审
    电压调节方法,应用处理器及具有相同功能的移动设备

    公开(公告)号:KR1020140033663A

    公开(公告)日:2014-03-19

    申请号:KR1020120099753

    申请日:2012-09-10

    Abstract: The dynamic voltage scaling method is capable of controlling a clock management unit to predict the operation status of the central processing unit to provide the operation frequency data representing the increase or decrease of the operation frequency of an application processor to an integrated power management circuit, and controlling the integrated power management circuit to alter the operation frequency of the application processor based on the operation frequency data provided from the clock management unit. [Reference numerals] (AA) Start; (BB) End; (S120) Clock management unit predicts the operation status of the central processing unit and provides the operation frequency data to an integrated power management circuit based on the predicted operation status; (S140) Integrated power management circuit changes the dynamic voltage of an application processor based on the operation frequency data

    Abstract translation: 动态电压缩放方法能够控制时钟管理单元来预测中央处理单元的操作状态,以将表示应用处理器的操作频率的增加或减少的操作频率数据提供给集成电源管理电路,以及 基于从时钟管理单元提供的操作频率数据,控制集成电源管理电路来改变应用处理器的操作频率。 (附图标记)(AA)开始; (BB)结束; (S120)时钟管理单元预测中央处理单元的操作状态,并且基于预测的操作状态将操作频率数据提供给集成功率管理电路; (S140)集成电源管理电路基于操作频率数据改变应用处理器的动态电压

    반도체 장치
    26.
    发明公开
    반도체 장치 无效
    半导体器件

    公开(公告)号:KR1020120110868A

    公开(公告)日:2012-10-10

    申请号:KR1020110029030

    申请日:2011-03-30

    CPC classification number: H03K19/017509

    Abstract: PURPOSE: A semiconductor device is provided to secure a stable operation by preventing the influence of a voltage variation between a plurality of function blocks or correcting the variation of an operation voltage by a shifting operation of a voltage level. CONSTITUTION: A first function block(FBLK1) generates a data signal by operating with a first operation voltage of a first range. A second function block(FBLK2) operates with a second operation of a second range. A voltage level control unit(LCU) differently shifts the voltage of the data signal according to a difference between the first operation voltage and the second operation voltage and transmits the shifted voltage to the second function block.

    Abstract translation: 目的:提供一种半导体器件,通过防止多个功能块之间的电压变化的影响或通过电压电平的移位操作来校正操作电压的变化来确保稳定的操作。 构成:第一功能块(FBLK1)通过以第一范围的第一操作电压进行操作来产生数据信号。 第二功能块(FBLK2)以第二范围的第二操作操作。 电压电平控制单元(LCU)根据第一操作电压和第二操作电压之间的差异不同地移位数据信号的电压,并将移位的电压发送到第二功能块。

    시스템 온 칩, 이를 포함하는 장치들, 및 상기 시스템 온 칩의 전력 제어 방법
    27.
    发明公开
    시스템 온 칩, 이를 포함하는 장치들, 및 상기 시스템 온 칩의 전력 제어 방법 审中-实审
    芯片系统,具有该芯片的设备以及SOC的功率控制方法

    公开(公告)号:KR1020110123698A

    公开(公告)日:2011-11-15

    申请号:KR1020110043094

    申请日:2011-05-06

    Abstract: PURPOSE: An SoC, apparatus including the same, and power control method thereof are provided to reduce the area of a power control circuit of an IC device and the complexity of an IC device by configuring a power control circuit having a power cluster and a center cluster. CONSTITUTION: An SoC(System on Chip) includes power area blocks(131-13n), a core, and a power control circuit(140). The power control circuit controls power which is supplied to power area blocks in response to the control of the core. The power control circuit includes power clusters(141-14n) corresponding to electricity field blocks and a center cluster(150). The power cluster controls the power supplied to the power area block. The center cluster controls the operating sequence of power clusters in response to the control of the core.

    Abstract translation: 目的:提供一种SoC,包括其的设备及其功率控制方法,通过配置具有功率簇和中心的功率控制电路来减少IC器件的功率控制电路的面积和IC器件的复杂性 簇。 构成:SoC(片上系统)包括功率区块(131-13n),核心和功率控制电路(140)。 功率控制电路响应于芯的控制而控制供应给功率区块的功率。 功率控制电路包括对应于电场块的功率簇(141-14n)和中心簇(150)。 电源组控制供电到电源区块的电源。 中心集群响应于核心的控制来控制功率集群的操作顺序。

    28.
    外观设计
    失效

    公开(公告)号:KR3000481290000S

    公开(公告)日:1984-07-23

    申请号:KR3019830009204

    申请日:1983-08-29

    Designer: 신택균

    29.
    外观设计
    失效

    公开(公告)号:KR3000481270000S

    公开(公告)日:1984-07-23

    申请号:KR3019830009202

    申请日:1983-08-29

    Designer: 신택균

    30.
    外观设计
    失效

    公开(公告)号:KR3000453400000S

    公开(公告)日:1983-12-29

    申请号:KR3019830004532

    申请日:1983-04-26

    Designer: 신택균

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