-
公开(公告)号：KR1020140057916A
公开(公告)日：2014-05-14
申请号：KR1020120124272
申请日：2012-11-05
Applicant: 삼성전자주식회사
CPC classification number: G06T15/205 , G06T7/32 , G06T19/006 , G06T2210/41
Abstract: An image processing apparatus is provided. A calculation unit of the image processing apparatus can calculate a first pose and a second pose from an input image, wherein the first pose is associated with an object included in an input image and a second pose is associated with a display device included in the input image and is separated from the object. A rendering unit of the image processing apparatus can render image data associated with the object to a result image based on the first pose and the second pose.
Abstract translation: 提供一种图像处理装置。 图像处理装置的计算单元可以从输入图像计算第一姿态和第二姿势，其中，第一姿态与包括在输入图像中的对象相关联，并且第二姿势与包括在输入中的显示装置相关联 图像并与对象分离。 图像处理装置的绘制单元可以基于第一姿态和第二姿势将与对象相关联的图像数据呈现到结果图像。
-
公开(公告)号：KR1020130048632A
公开(公告)日：2013-05-10
申请号：KR1020110113590
申请日：2011-11-02
Applicant: 삼성전자주식회사
IPC: H03K19/0175 , H03K5/13
CPC classification number: H03L7/0814
Abstract: PURPOSE: A clock buffer circuit and a data output circuit including the same are provided to distribute an EMI energy component generating in a harmonic frequency component by randomly varying a frequency and a duty of a clock signal. CONSTITUTION: A clock buffer circuit(10) includes a buffer unit(100), a delay control unit(120) and a delay unit(140). The buffer unit receives an input clock signal and generates an internal clock signal and a first clock signal. The delay control unit receives the internal clock signal from the buffer unit and generates a control signal in response to a first control signal and second control signal. The delay unit generates a second clock signal in response to the first clock signal transmitted from the buffer unit and the delay control signal transmitted from the delay control unit. The delay unit generates a second clock signal by randomly controlling a transmission delay time of the first clock signal.
Abstract translation: 目的：提供时钟缓冲电路和包括该时钟缓冲电路的数据输出电路，通过随机改变时钟信号的频率和占空比来分配产生谐波频率分量的EMI能量分量。 构成：时钟缓冲电路（10）包括缓冲单元（100），延迟控制单元（120）和延迟单元（140）。 缓冲单元接收输入时钟信号并产生内部时钟信号和第一时钟信号。 延迟控制单元从缓冲单元接收内部时钟信号，并响应于第一控制信号和第二控制信号产生控制信号。 延迟单元响应于从缓冲单元发送的第一时钟信号和从延迟控制单元发送的延迟控制信号产生第二时钟信号。 延迟单元通过随机地控制第一时钟信号的传输延迟时间来产生第二时钟信号。
-
公开(公告)号：KR1020130045144A
公开(公告)日：2013-05-03
申请号：KR1020120017823
申请日：2012-02-22
Applicant: 삼성전자주식회사
CPC classification number: G11C7/1051 , G11C7/06 , G11C7/22 , G11C2207/105 , H03K19/01721
Abstract: PURPOSE: An output driver, devices including the same, and a ground termination are provided to process data at high speed by using an NMOS transistor instead of a PMOS transistor. CONSTITUTION: An integrated circuit includes an output driver(100A) and a receiving circuit. The output driver includes an output terminal. The receiving circuit includes a termination resistance between the output terminal and a ground. The output driver includes a first NMOS transistor(101) and a second NMOS transistor(103). The first NMOS transistor pulls up the output terminal with a pull-up voltage in response to a pull-up signal. The second NMOS transistor pulls down the output terminal in response to a pull-down signal.
Abstract translation: 目的：通过使用NMOS晶体管代替PMOS晶体管，提供输出驱动器，包括相同的器件和接地端接器来高速处理数据。 构成：集成电路包括输出驱动器（100A）和接收电路。 输出驱动器包括输出端子。 接收电路包括输出端和接地之间的终端电阻。 输出驱动器包括第一NMOS晶体管（101）和第二NMOS晶体管（103）。 第一个NMOS晶体管响应上拉信号，以一个上拉电压上拉输出端。 第二NMOS晶体管响应于下拉信号而拉下输出端。
-
公开(公告)号：KR1020120091589A
公开(公告)日：2012-08-20
申请号：KR1020110011447
申请日：2011-02-09
Applicant: 삼성전자주식회사
IPC: G06T1/00 , G06T9/00 , H04N19/20 , H04N19/436
CPC classification number: G06T15/00 , G06T9/00 , H04N19/20 , H04N19/436 , G06T1/00
Abstract: PURPOSE: A graphic processing device for compressing and decompressing data and a method thereof are provided to reduce bottle neck phenomena between a central processing unit and the graphic processing device. CONSTITUTION: A segment information extracting unit(210) analyzes a compression data header in a bit stream of compression data received from a central processing unit. The segment information extracting unit extracts segment data. A decompressing unit(250) decompresses segments of the bit stream in parallel based on the segment data.
Abstract translation: 目的：提供一种用于压缩和解压缩数据的图形处理装置及其方法，以减少中央处理单元和图形处理装置之间的瓶颈现象。 构成：段信息提取单元（210）分析从中央处理单元接收的压缩数据的比特流中的压缩数据头。 段信息提取单元提取段数据。 解压缩单元（250）基于段数据并行解压缩位流的段。
-
公开(公告)号：KR1020120085066A
公开(公告)日：2012-07-31
申请号：KR1020110006468
申请日：2011-01-21
Applicant: 삼성전자주식회사 , 고려대학교 산학협력단
CPC classification number: G06T9/001 , G06T9/004 , G06T17/205 , G06T15/00 , H04N19/50
Abstract: PURPOSE: A data processing device and a method thereof are provided to efficiently compress location information of a vertex which configures a 3D object. CONSTITUTION: A vertex partitioning unit(120) partitions a plurality of vertexes into one or more groups. The vertexes are included in a 3D object. A prediction mode determining unit(130) determines a location prediction mode for compressing a vertex location for at least one group. An encoding unit(140) encodes an identification index of the determined prediction mode and a prediction error vector for at least one group.
Abstract translation: 目的：提供一种数据处理设备及其方法，用于有效地压缩配置3D对象的顶点的位置信息。 构成：顶点分割单元（120）将多个顶点分割成一个或多个组。 顶点包含在3D对象中。 预测模式确定单元（130）确定用于压缩至少一个组的顶点位置的位置预测模式。 编码单元（140）对所确定的预测模式的识别索引和至少一个组的预测误差向量进行编码。
-
Patent Agency Ranking
公开(公告)号：KR102250254B1
公开(公告)日：2021-05-10
申请号：KR1020140101172
申请日：2014-08-06
Applicant: 삼성전자주식회사
IPC: G06T15/00
Abstract: 영상처리장치및 방법이개시된다. 일실시예에따르면, 영상처리장치는이전영상프레임의가상광원정보에기초하여현재영상프레임의특정영역에서가상광원이샘플링되는것을방지하기위한마스크를생성할수 있다. 영상처리장치는마스크를현재영상프레임에적용하여영상처리장치는시간적으로연속성을가지는영상프레임들사이에서가상광원이중복적으로샘플링되는것을방지할수 있다. 영상처리장치는이전영상프레임에서샘플링된가상광원을현재영상프레임에반영하고, 추가적으로샘플링된가상광원들에기초하여현재영상프레임을렌더링할수 있다.
-
-
-
-
公开(公告)号：KR102020026B1
公开(公告)日：2019-09-09
申请号：KR1020130012154
申请日：2013-02-04
Applicant: 삼성전자주식회사
IPC: H04N21/436 , G02F1/1333 , H04N21/44 , H04N21/2365
-
-
-
-
-
-
-
-
-
Search Results
77
records
(took 0.023 seconds)
