公开(公告)号：KR102229942B1

公开(公告)日：2021-03-22

申请号：KR1020140086188A

申请日：2014-07-09

Applicant: 삼성전자주식회사

Inventor： 엄윤주 ,  박준영 ,  배용철 ,  이원영 ,  장성진 ,  최정환 ,  최주선

IPC: G11C5/02 ,  G11C7/10

CPC classification number: G11C11/4096 ,  G11C11/4093 ,  G11C7/1084 ,  G11C2207/105

Abstract: 멀티 채널 반도체 장치가 개시된다. 그러한 멀티 채널 반도체 장치는 제1 칩으로서 기능하기 위해 제1 채널을 가지는 제1 다이와 제2 칩으로서 기능하기 위해 상기 제1 채널과는 독립적인 제2 채널을 가지며, 저장 용량 및 사이즈가 상기 제1 다이와 동일한 제2 다이를 구비한다. 상기 제1 다이와 상기 제2 다이 간에는 서로 상대되는 칩들로 상기 제1,2 다이들의 내부 동작을 제어하기 위한 정보를 전달하기 위한 내부 인터페이스가 동일 패키지 내에서 배치된다. 본 발명에 따르면 내부 인터페이스를 통해 카운터파트 다이로 정보가 전달된다. 따라서, 제조 수율이 개선된다.

公开(公告)号：KR101906407B1

公开(公告)日：2018-10-10

申请号：KR1020120033938

申请日：2012-04-02

Applicant: 삼성전자주식회사

Inventor： 엄윤주 ,  전영진 ,  배용철 ,  조영철

IPC: G11C7/10 ,  G11C5/14

Abstract: 채널환경및 메모리컨트롤러의온 다이터미네이션저항의미스매치를고려하여출력전압의레벨을보정하는반도체메모리장치및 이를포함하는메모리시스템이개시된다. 메모리시스템은메모리컨트롤러및 반도체메모리장치를포함한다. 반도체메모리장치는메모리컨트롤러의구동정보에기초하여기준전압을발생하고, 메모리컨트롤러와전기적으로연결된상태에서기준전압에기초하여출력전압레벨을보정한다. 따라서, 반도체메모리장치는신호충실도가향상되고전력소모가적다.

公开(公告)号：KR1020140005399A

公开(公告)日：2014-01-15

申请号：KR1020120069453

申请日：2012-06-27

Applicant: 삼성전자주식회사

Inventor： 조영철 ,  배용철 ,  엄윤주 ,  전영진

IPC: H03K19/0175 ,  H03F3/45

CPC classification number: H03F3/45179 ,  G11C7/06 ,  G11C7/10 ,  G11C7/1084 ,  H03F3/45237 ,  H03F3/45672 ,  H03F2203/45296 ,  H03F2203/45316 ,  H03F2203/45328 ,  H03F2203/45358 ,  H03F2203/45372 ,  H03F2203/45431 ,  H03F2203/45506

Abstract: A self-bias operational amplifier and a small signal receiver including the same are provided. The small signal receiver according to an embodiment of the present invention includes: a first current regulating circuit which is connected between a first power source voltage (VDD) terminal and a first node (N1) and supplies a current in response to a self-bias signal; the self-biased operational amplifier which is connected between the first node and a second node, supplies the self-bias signal to a self-bias node (N3) by comparing an input signal with a reference voltage, and outputs an output signal through an output node; and a second current regulating circuit which is connected between the second node (N5) and a second power source voltage (VSS) and synchronizes the current of the second node in response to the self-bias signal. The self-bias operational amplifier includes a swing stabilization block which is connected between an input node in which the input signal is applied and the self-bias node and stabilizes the input signal which is compared with the reference voltage.

Abstract translation: 提供了自偏压运算放大器和包括其的小信号接收器。 根据本发明实施例的小信号接收机包括：第一电流调节电路，连接在第一电源电压（VDD）端和第一节点（N1）之间，并响应于自偏压提供电流 信号; 连接在第一节点和第二节点之间的自偏置运算放大器通过将输入信号与参考电压进行比较来将自偏置信号提供给自偏压节点（N3），并通过 输出节点; 以及连接在第二节点（N5）和第二电源电压（VSS）之间的第二电流调节电路，并且响应于自偏置信号使第二节点的电流同步。 自偏压运算放大器包括摆动稳定块，其连接在其中施加输入信号的输入节点和自偏压节点之间，并稳定与参考电压进行比较的输入信号。

公开(公告)号：KR1020130112744A

公开(公告)日：2013-10-14

申请号：KR1020130023896

申请日：2013-03-06

Applicant: 삼성전자주식회사

Inventor： 조영철 ,  엄윤주 ,  전영진 ,  배용철

IPC: G11C7/10 ,  H03K19/0185

CPC classification number: G11C7/1078 ,  G11C7/06 ,  G11C8/10 ,  H03F3/45179

Abstract: PURPOSE: An input receiving circuit including a single-to-differential amplifier and a semiconductor device including the same operate at high speed by including a first stage amplifier unit with a single-to-differential amplification method. CONSTITUTION: A first stage amplifier unit (110) amplifies a single input signal with a single-to-differential method and generates a differential output signal. A second stage amplifier unit (150) amplifies the differential output signal with a differential-to-single method and generates a single output signal. A common source amplifier receives an input voltage signal by a gate terminal, amplifies the input voltage signal, and outputs the amplified voltage signal to a drain terminal. A common gate amplifier receives the input voltage signal by a source terminal (or a drain terminal), amplifies the input voltage signal, and outputs the amplified signal to the drain terminal (or the source terminal).

Abstract translation: 目的：包括单差分放大器和包括其的半导体器件的输入接收电路通过包括具有单差分放大方法的第一级放大器单元在高速下工作。 构成：第一级放大器单元（110）用单差分方法放大单个输入信号，并产生差分输出信号。 第二级放大器单元（150）以差分到单个方法放大差分输出信号，并产生单个输出信号。 公共源放大器通过栅极端子接收输入电压信号，放大输入电压信号，并将放大的电压信号输出到漏极端子。 公共栅极放大器由源极端子（或漏极端子）接收输入电压信号，放大输入电压信号，并将放大的信号输出到漏极端子（或源极端子）。

公开(公告)号：KR100496786B1

公开(公告)日：2005-09-14

申请号：KR1019970036639

申请日：1997-07-31

Applicant: 삼성전자주식회사

Inventor： 배용철 ,  위성민

IPC: G11C11/407

Abstract: 본 발명은 에 관한 것으로서, 더 구체적으로는 내부 신호들의 마진을 검사하는 반도체 메모리 장치에 관한 것으로서, 행방향으로 배열되는 워드 라인들을 나누어 구동하는 서브 워드 라인 구동 장치를 갖는 반도체 메모리 장치에 있어서, 로우 어드레스 스트로브 신호가 프리챠지 구간일 때의 신호를 인가받아 이를 지연시켜 제 1 워드 라인 제어 신호를 출력하는 제 1 지연 수단과; 상기 로우 어드레스 스트로브 신호가 프리챠지 구간일 때의 로우 어드레스 스트로브 신호를 인가받고, 이를 지연시켜 제 1 내부 제어 신호를 출력하는 제 2 지연 수단과; 상기 제 1 내부 제어 신호와 외부 제어 신호를 인가받고, 상기 제 1 내부 제어 신호가 하이레벨일때 도 비활성화되는 제 2 내부 제어 신호를 발생하는 마진 제어 수단과; 상기 비활성화되는 제 2 내부 제어 신호를 인가받아 지연된 제 2 워드 라인 제어 신호를 발생하는 제 3 지연 수단과; 외부로부터 전원 전압을 인가받고, 상기 제 1 워드 라인 제어 신호 및 제 2 워드 라인 제어 신호에 따라 복수 개의 워드 라인들을 나누어 구동 시키는 서브 워드 라인 구동 수단을 포함하는 반도체 메모리 장치.

公开(公告)号：KR1020010084281A

公开(公告)日：2001-09-06

申请号：KR1020000009178

申请日：2000-02-24

Applicant: 삼성전자주식회사

Inventor： 배용철

IPC: G11C7/12

CPC classification number: G11C7/22 ,  G11C8/18

Abstract: PURPOSE: A circuit for generating an auto precharge control signal and an auto precharge control method of a semiconductor memory device are provided, which prevent the generation of unnecessary auto precharge control signal by the crossing of a 1 clock delay signal and a column bank address signal during a continuous burst write operation. CONSTITUTION: The circuit includes an output enable unit(100), a delay unit(200) and an assembly unit(300). The output enable unit is reset in response to a precharge operation and generates an output enable signal by latching an auto precharge command signal in an active interval of a column bank address signal. The output enable unit includes a switching unit(110), an inversion latch unit(120), a reset unit(130) and a precharge reset signal generation unit(140). The delay unit generates a 1 clock delay signal by delaying an active interval of the column bank address signal by 1 clock, and generates a 1 clock delay signal having an active interval including a nonactive interval between a prior column bank address signal and a present column bank address signal in case that a burst length is 1. The delay unit includes an input latch unit(210), a clock synchronization latch unit(220) and an auto pulse generation unit(230). The assembly unit includes a NOR gate(NOR2) to perform a NOR operation of the 1 clock delay signal and the column bank address signal, and a NAND gate(NAND4) to perform a NAND operation of an output signal of the NOR gate and the output enable signal.

Abstract translation: 目的：提供一种用于产生半导体存储器件的自动预充电控制信号和自动预充电控制方法的电路，其防止通过1个时钟延迟信号和列组地址信号的交叉产生不必要的自动预充电控制信号 在连续的突发写入操作期间。 构成：电路包括输出使能单元（100），延迟单元（200）和组装单元（300）。 输出使能单元响应于预充电操作被复位，并通过在列组地址信号的有效间隔中锁存自动预充电命令信号来产生输出使能信号。 输出使能单元包括开关单元（110），反相锁存单元（120），复位单元（130）和预充电复位信号生成单元（140）。 延迟单元通过将列组地址信号的有效间隔延迟1个时钟来产生1个时钟延迟信号，并且产生具有有效间隔的1个时钟延迟信号，该有效间隔包括现有列组地址信号和当前列之间的非有效间隔 在突发长度为1的情况下，存储器地址信号。延迟单元包括输入锁存单元（210），时钟同步锁存单元（220）和自动脉冲生成单元（230）。 组合单元包括用于执行1个时钟延迟信号和列组地址信号的NOR运算的NOR门（NOR2），以及与非门（NAND4）进行NAND门和/或非门的输出信号的NAND运算 输出使能信号。

公开(公告)号：KR1020010077080A

公开(公告)日：2001-08-17

申请号：KR1020000004643

申请日：2000-01-31

Applicant: 삼성전자주식회사

Inventor： 배용철 ,  이중화

IPC: G11C11/4091

CPC classification number: G11C7/1006 ,  G11C7/1048 ,  G11C11/4096 ,  G11C7/1018 ,  G11C8/18 ,  G11C11/408

Abstract: PURPOSE: A burst-type semiconductor memory device having full page mode is provided, which has pre-charge scheme for charging the first and second input/output buses between a write operation section through the first input/output bus arranged at one side of an array and a write operation section through the second input/output bus arranged at the other side during full page mode. CONSTITUTION: A semiconductor memory device includes a memory cell array(100) having a plurality of memory cells(110), a plurality of word lines(WLi) and a plurality of bit line pairs(BLj,BLjB), the first and second input/output buses arranged at both sides of the memory cell array, and a plurality of column select lines(CSL0-CSLk) for simultaneously selecting the first and second input/output buses. The semiconductor memory device further has a pre-charge circuit for charging the first and second input/output buses with a predetermined voltage in response to a pre-charge signal during full-page mode, and a pre-charge controller(150) for generating the pre-charge signal during the full-page mode. The pre-charge controller generates the pre-charge signal having the shape of pulse between the first section during which data is written into the array through the first input/output bus during the (N-1)th cycle of a clock signal and the second section during which data is written into the array through the second input/output bus during the Nth cycle of the cock signal.

Abstract translation: 目的：提供具有全页模式的突发型半导体存储器件，其具有用于对第一和第二输入/输出总线在通过布置在 阵列和写入操作部分，通过在全页模式下布置在另一侧的第二输入/输出总线。 构成：半导体存储器件包括具有多个存储单元（110），多个字线（WLi）和多个位线对（BLj，BLjB）的存储单元阵列（100），第一和第二输入 布置在存储单元阵列两侧的输出总线和用于同时选择第一和第二输入/输出总线的多个列选择线（CSL0-CSLk）。 半导体存储器件还具有预充电电路，用于响应于全页模式期间的预充电信号，以预定电压对第一和第二输入/输出总线充电;以及预充电控制器（150），用于产生 在全页模式期间的预充电信号。 预充电控制器在时钟信号的第（N-1）周期期间产生具有第一部分之间的脉冲形状的预充电信号，在第一部分期间通过第一输入/输出总线将数据写入阵列， 第二部分，其中在旋转信号的第N个周期期间，数据通过第二输入/输出总线写入阵列。

公开(公告)号：KR1020010009808A

公开(公告)日：2001-02-05

申请号：KR1019990028400

申请日：1999-07-14

Applicant: 삼성전자주식회사

Inventor： 배용철 ,  이중화

IPC: G11C7/00

CPC classification number: G11C7/1048

Abstract: PURPOSE: An equalization circuit is provided to improve a precharge speed and to minimize a drop in efficiency of a lay-out and a memory device having the equalization circuit. CONSTITUTION: An equalization circuit is embedded in a memory device. The memory device has the first and second memory blocks(110,210) one of which is selected by the first or second block selection signal. The equalization circuit(170,180) includes an equalization control circuit(172) and an equalization portion(120,220). The equalization control circuit receives a precharge signal and generates an equalization control signal in response to the first and second equalization signals selectively activated by the first or second block selection signal. The equalization control circuit has the first transmission gate outputting the precharge signal in response to the first equalization signal, and the second transmission gate outputting the precharge signal in response to the second equalization signal. The equalization portion is arranged an input/output line pair and equalizes the input/output line pair in a constant voltage when the equalization control signal becomes active.

Abstract translation: 目的：提供均衡电路以提高预充电速度并最小化具有均衡电路的布局和存储器件的效率下降。 构成：将均衡电路嵌入存储器件中。 存储器件具有第一和第二存储器块（110,210），其中之一由第一或第二块选择信号选择。 均衡电路（170,180）包括均衡控制电路（172）和均衡部分（120,220）。 均衡控制电路响应于由第一或第二块选择信号有选择地激活的第一和第二均衡信号，接收预充电信号并产生均衡控制信号。 均衡控制电路具有响应于第一均衡信号而输出预充电信号的第一传输门，并且响应于第二均衡信号，第二传输门输出预充电信号。 均衡部分配置有输入/输出线对，当均衡控制信号变为有效时，使恒流输入/输出线对平衡。

公开(公告)号：KR100238238B1

公开(公告)日：2000-01-15

申请号：KR1019970011830

申请日：1997-03-31

Applicant: 삼성전자주식회사

Inventor： 윤세승 ,  배용철

IPC: G11C5/14

CPC classification number: G11C7/1051 ,  G11C7/1006

Abstract: In a semiconductor memory device, a plurality of output buffers, one for each output data bit, are powered by an internal voltage control circuit so as to provide high speed operation yet minimize power consumption. The internal voltage control circuit inclues multiple internal voltage generators. Responsive to the number of output buffers in use during a read operation, one or more of the voltage generators are activated to power the output buffers. Additionally, the current capacity of each of the individual voltage generators is controlled responsive to the number of output buffers in use during the read operation, so that bandwidth of the memory device is maximized but power is not wasted.

公开(公告)号：KR1019990065747A

公开(公告)日：1999-08-05

申请号：KR1019980001181

申请日：1998-01-16

Applicant: 삼성전자주식회사

Inventor： 배용철 ,  김기홍

IPC: G11C5/14

Abstract: 안정된 내부전원전압 구동 드라이버의 출력을 갖는 반도체 메모리장치가 개시된다. 상기 반도체 메모리장치는, 메모리셀 어레이 블락, 상기 메모리셀 어레이 블락으로부터 피드백되는 내부전원전압 및 기준전압을 입력으로 하는 차동증폭기, 상기 차동증폭기의 출력에 응답하여 상기 메모리셀 어레이 블락에 내부전원전압을 제공하는 내부전원전압 구동 드라이버, 제어신호에 응답하여 상기 차동증폭기의 출력단을 풀다운시키는 풀다운 수단, 및 상기 제어신호를 발생하는 제어신호 발생수단을 구비하는 것을 특징으로 한다.