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公开(公告)号：KR1020030061152A
公开(公告)日：2003-07-18
申请号：KR1020020001683
申请日：2002-01-11
Applicant: 삼성전자주식회사
IPC: H01L23/544
Abstract: PURPOSE: A method for manufacturing a semiconductor package is provided to be capable of improving the UPEH(Unit Per Equipment Hour) of the semiconductor package by additionally forming the mark of company name under a molding process. CONSTITUTION: A wafer fabrication is carried out for forming a chip(S100). A wire bonding process is carried out for bonding the chip on a lead frame(S200). A semiconductor package is formed by carrying out a molding process using resin while marking company name on one surface of the semiconductor package(S300). A forming process is carried out for bending a lead exposed from the package(S500). A test is carried out for inspecting the electrical operation state of the package(S700). A marking process is carried out on the surface of the package(S800). An auto inspection is carried out for inspecting the appearance of the package(S900).
Abstract translation: 目的：提供一种制造半导体封装的方法，其能够通过在模制工艺下额外形成公司名称的标记来改善半导体封装的UPEH（单位每设备小时）。 构成：进行用于形成芯片的晶片制造（S100）。 进行引线接合处理以将芯片接合在引线框架上（S200）。 通过在半导体封装的一个表面上标记公司名称的同时执行使用树脂的模制工艺来形成半导体封装（S300）。 进行用于弯曲从封装暴露的引线的成形工艺（S500）。 进行用于检查包装的电气运行状态的测试（S700）。 在包装的表面上进行标记处理（S800）。 进行自动检查以检查包装的外观（S900）。
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公开(公告)号：KR1020090008515A
公开(公告)日：2009-01-22
申请号：KR1020070071508
申请日：2007-07-18
Applicant: 삼성전자주식회사
Abstract: A film structure for cutting a wafer, a wafer cutting method using the same, and a method for manufacturing a semiconductor module are provided to improve reliability of electrical connection between a semiconductor chip and a printed circuit board by integrating the semiconductor chip with the printed circuit board by using an adhesive film. Pads(210) are formed on a first side of a wafer(200). A release film(120) is adhered on the first side of the wafer. A base film(110) is adhered on a second side of the wafer. An adhesive film(130) is adhered on the release film. A cover film(140) is adhered on the adhesive film. The adhesive film includes thermosetting resin to be cut by an ultraviolet ray.
Abstract translation: 提供用于切割晶片的薄膜结构，使用该薄膜结构的晶片切割方法以及制造半导体模块的方法，以通过将半导体芯片与印刷电路集成来提高半导体芯片和印刷电路板之间的电连接的可靠性 通过使用粘合膜进行印刷。 垫片（210）形成在晶片（200）的第一侧上。 剥离膜（120）粘附在晶片的第一侧上。 基膜（110）粘附在晶片的第二面上。 粘合膜（130）粘附在剥离膜上。 覆盖膜（140）粘附在粘合膜上。 粘合膜包括用紫外线切割的热固性树脂。
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公开(公告)号：KR100833187B1
公开(公告)日：2008-05-28
申请号：KR1020060107943
申请日：2006-11-02
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L24/85 , H01L23/4952 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4846 , H01L2224/48471 , H01L2224/48475 , H01L2224/48479 , H01L2224/48599 , H01L2224/48644 , H01L2224/48699 , H01L2224/48744 , H01L2224/49111 , H01L2224/78301 , H01L2224/85051 , H01L2224/85205 , H01L2224/85444 , H01L2224/85986 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2224/85186 , H01L2924/00 , H01L2224/48227 , H01L2924/00015 , H01L2224/4554
Abstract: 루프 높이를 현저히 낮출 수 있으며, 결합 신뢰성이 향상되는 반도체 패키지의 와이어 본딩 방법이 개시된다. 본 발명의 와이어 본딩 방법은, 와이어를 공급할 수 있는 캐필러리를 사용하여 반도체 칩 상에 형성된 본딩 패드에 볼 범프를 형성한 후, 상기 캐필러리가 상기 볼 범프로부터 상기 와이어를 절단한다. 이어서 상기 캐필러리를 상기 반도체 칩의 본딩 패드와 대응하는 배선으로 이동하여 상기 배선 상에 상기 캐필러리로부터 공급되는 와이어를 스티치 본딩(stitch bonding)한다. 다시 상기 캐필러리를 상기 본딩 패드에 형성된 상기 볼 범프 위로 이동한 후 상기 볼 범프 상에 상기 와이어를 본딩한다.
루트, 패키지, 캐필러리, 본딩, 범프, 폴딩-
公开(公告)号：KR1020070079654A
公开(公告)日：2007-08-08
申请号：KR1020060010460
申请日：2006-02-03
Applicant: 삼성전자주식회사
CPC classification number: H01L2224/16 , H01L21/563 , H01L21/0273 , H01L21/76838 , H01L21/76897 , H01L23/28 , H01L23/49816
Abstract: A PCB for flip chip bonding and a ball grid array package manufacturing method using the same are provided to shorten an input/output path by mounting a semiconductor chip thereon in a flip chip bonding method. A board body(10) has an upper surface, a lower surface, and a thickness. A metal wiring layer(20) is formed on the upper and lower surfaces of the board body. The metal wiring layer includes a substrate pad(22) formed on the upper surface of the board body and a terminal pad(24) formed on the lower surface of the board body. A via hole(30) is formed in a vertical direction of the board body to connect electrically the metal wiring layers of the upper and lower surfaces. A photo solder resist(40) is formed to cover the metal wiring layer except for the substrate pad and the terminal pad. A plated layer(50) is formed on the substrate pad. A solder layer(60) is formed on the plated layer.
Abstract translation: 提供了一种用于倒装芯片接合的PCB和使用该PCB的球栅阵列封装制造方法，以通过以倒装芯片接合方法将半导体芯片安装在其上来缩短输入/输出路径。 板体（10）具有上表面，下表面和厚度。 金属布线层（20）形成在板体的上表面和下表面上。 金属布线层包括形成在基板主体的上表面上的基板焊盘（22）和形成在基板主体的下表面上的端子焊盘（24）。 在板体的垂直方向上形成通孔（30），以电连接上表面和下表面的金属布线层。 形成光阻焊剂（40）以覆盖基板焊盘和端子焊盘以外的金属布线层。 在基板焊盘上形成镀层（50）。 在镀层上形成焊料层（60）。
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公开(公告)号：KR100669830B1
公开(公告)日：2007-04-16
申请号：KR1020040093479
申请日：2004-11-16
Applicant: 삼성전자주식회사
Abstract: 본 발명은 이방성 도전막을 이용한 적층 패키지에 관한 것으로, CSP를 적층할 때 CSP에 작용하는 열적 스트레스를 최소화하고, CSP의 손상 없이 적층 패키지에 대한 수리 공정을 용이하게 진행하기 위해서, 배선기판과, 상기 배선기판의 상부면에 실장되어 상기 배선기관과 전기적으로 연결된 반도체 칩과, 상기 반도체 칩 외측의 상기 배선기판의 하부면에 형성된 솔더 볼들을 포함하는 칩 스케일 패키지들을 3차원으로 적층한 적층 패키지에 있어서, 피적층 칩 스케일 패키지의 배선기판 상부면의 반도체 칩 외곽에 개재되어 적층 칩 스케일 패키지의 솔더 볼을 상기 피적층 칩 스케일 패키지의 배선기판에 적층 및 전기적으로 연결하는 열가소성의 이방성 도전막을 포함하는 것을 특징으로 하는 이방성 도전막을 이용한 적층 패키지를 제공한다.
이방성, ACF, CSP, 적층, 패키지Abstract translation: 本发明涉及一种堆叠式封装使用各向异性导电膜，以便当堆叠CSP最小化热应力作用于CSP并前进到促进多层封装的修复过程，以避免CSP，布线板，包括损害： 在一个它被安装在电路板堆叠的芯片级封装，其包括和布线发动机和半导体芯片电连接到形成在3-d堆叠封装外部的半导体芯片的电路板的下表面上的焊料球的上表面 ，它包括要被层叠设置在所述堆叠的芯片级封装的焊球的芯片级封装的电路板顶面的外侧的半导体芯片上，所述待层压堆叠在芯片规模封装的布线板，并电热塑性各向异性导电膜连接 提供使用各向异性导电膜的层压封装。
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Patent Agency Ranking
公开(公告)号：KR1020070025624A
公开(公告)日：2007-03-08
申请号：KR1020050081992
申请日：2005-09-03
Applicant: 삼성전자주식회사
CPC classification number: H01L24/73 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
Abstract: A semiconductor package and its fabrication method are provided to restrain the degradation of reliability in the semiconductor package by preventing the deformation of the semiconductor package using an adhesive member exposed to the outside through a molding member. A semiconductor chip(300) is mounted on a substrate(100). An adhesive member(200) is used for connecting the semiconductor chip to the substrate. A wiring(400) is used for connecting electrically the semiconductor chip with the substrate. A molding member(500) is used for enclosing the semiconductor chip and the wiring. The adhesive member is partially exposed to the outside through the molding member.
Abstract translation: 提供一种半导体封装及其制造方法，以通过使用通过模制构件暴露于外部的粘合构件来防止半导体封装的变形来抑制半导体封装中的可靠性的劣化。 半导体芯片（300）安装在基板（100）上。 粘合剂（200）用于将半导体芯片连接到基板上。 布线（400）用于将半导体芯片与基板电连接。 模制构件（500）用于封装半导体芯片和布线。 粘合剂部件通过模制部件部分地暴露于外部。
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公开(公告)号：KR1020020012955A
公开(公告)日：2002-02-20
申请号：KR1020000046231
申请日：2000-08-09
Applicant: 삼성전자주식회사
Inventor： 정용진
IPC: H01L21/82
Abstract: PURPOSE: A method for etching a fuse cutting hole is provided to simplify a manufacturing process by continuously etching an insulation layer and a polysilicon layer in an etch apparatus by an in-situ method, and to uniformly maintain the thickness of the insulation layer left on a fuse by using the polysilicon layer as an etch stop layer. CONSTITUTION: A plurality of insulation layers on a bit line fuse cutting hole are selectively etched in the apparatus for etching the insulation layer by using a plate polysilicon layer(112) as an etch stop layer. The plate polysilicon layer exposed by etching the insulation layer in the etch apparatus is etched.
Abstract translation: 目的：提供一种用于蚀刻保险丝切割孔的方法，以通过原位法在蚀刻装置中连续蚀刻绝缘层和多晶硅层来简化制造工艺，并且均匀地保持绝缘层的厚度保持 通过使用多晶硅层作为蚀刻停止层的熔丝。 构成：通过使用板状多晶硅层（112）作为蚀刻停止层，在用于蚀刻绝缘层的装置中选择性地蚀刻位线熔丝切割孔上的多个绝缘层。 通过蚀刻蚀刻装置中的绝缘层而露出的板状多晶硅层被蚀刻。
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公开(公告)号：KR1020010068733A
公开(公告)日：2001-07-23
申请号：KR1020000000790
申请日：2000-01-08
Applicant: 삼성전자주식회사
IPC: H01L27/085
Abstract: PURPOSE: A method for forming a CMOS transistor is provided to simplify process and reduce costs by removing an etching process for forming a spacer. CONSTITUTION: The method forms a CMOS transistor to a peripheral area of a semiconductor substrate(100) on which a P-well and a N-well are formed. The first step of the method is to form a gate oxide film(140) on a semiconductor substrate in which each well is formed. The second step is to form gate patterns for a PMOS and a NMOS on the upper of the N- and P-wells respectively. The third step is to form an insulating film for a conformal spacer on each of the gate patterns and the gate oxide film. The fourth step is to form a conductive film for forming a cell pad on the insulating film for the spacer. The fifth step is to remove the conductive film for forming the cell pad using an anisotropic etch and simultaneously leave the conductive film to thickness less than about 200Å by etching a part of the conductive film for the spacer on the gate insulating film(240b). The sixth step is to complete PMOS and NMOS transistors by implanting ions on the insulating film for the spacer remaining on the gate insulating film using the insulating film for the spacer formed on the each gate pattern, side wall thereof and upper thereof as a mask.
Abstract translation: 目的：提供用于形成CMOS晶体管的方法，以通过去除用于形成间隔物的蚀刻工艺来简化工艺并降低成本。 构成：该方法在其上形成有P阱和N阱的半导体衬底（100）的外围区域形成CMOS晶体管。 该方法的第一步是在其中形成每个阱的半导体衬底上形成栅极氧化膜（140）。 第二步是分别在N阱和P阱的上部形成用于PMOS和NMOS的栅极图案。 第三步是在每个栅极图案和栅极氧化膜上形成用于保形隔离物的绝缘膜。 第四步是在用于间隔物的绝缘膜上形成用于形成电池垫的导电膜。 第五步是使用各向异性蚀刻去除用于形成电池垫的导电膜，同时通过蚀刻用于栅绝缘膜（240b）上的间隔物的导电膜的一部分，同时使导电膜的厚度小于约200。 第六步是通过使用在每个栅极图案，其侧壁和其上部形成的间隔物的绝缘膜作为掩模，在留在栅极绝缘膜上的间隔物的绝缘膜上注入离子来完成PMOS和NMOS晶体管。
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公开(公告)号：KR1020010038739A
公开(公告)日：2001-05-15
申请号：KR1019990046849
申请日：1999-10-27
Applicant: 삼성전자주식회사
IPC: H01L21/335
Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to prevent a bridge caused by a micro stringer on a landing pad and to improve reliability, by preventing damage to an insulating layer spacer surrounding a gate region. CONSTITUTION: An interlayer dielectric(112) is formed on a semiconductor substrate(100) having an access transistor. A predetermined region of the interlayer dielectric is etched to form an opening exposing a part of the semiconductor substrate on an optimum etching condition that an insulating layer spacer(110) covering a gate region of the access transistor is not damaged. A conductive layer is deposited on the resultant structure having the opening, and patterned to form a landing pad(114) for interconnection.
Abstract translation: 目的：提供一种制造半导体器件的方法，以防止由于在栅极区域周围的绝缘层间隔件的损坏而导致由着陆焊盘上的微型纵梁引起的桥梁并提高可靠性。 构成：在具有存取晶体管的半导体衬底（100）上形成层间电介质（112）。 蚀刻层间电介质的预定区域，以形成在覆盖存取晶体管的栅极区域的绝缘层间隔物（110）不被损坏的最佳蚀刻条件下暴露半导体衬底的一部分的开口。 导电层沉积在具有开口的所得结构上，并被图案化以形成用于互连的着陆焊盘（114）。
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公开(公告)号：KR100267009B1
公开(公告)日：2000-09-15
申请号：KR1019970060885
申请日：1997-11-18
Applicant: 삼성전자주식회사
Inventor： 정용진
IPC: G06F7/44
CPC classification number: G06F7/722
Abstract: PURPOSE: A modular multiplying apparatus having an array structure for a high speed encryption is provided to implement a high speed modular multiplication by significantly decreasing a computation amount of an MSB. CONSTITUTION: Two nodes of each row are combined as one node, and regularity is maintained between arrays. An array structure adapted to VLSI is obtained. Nodes X1, X2 and X3 are nodes for obtaining a function. Nodes AA, BB and CC are nodes duplicated by nodes A, B and C by two. The node combination implements a linear structure and an easier hardware of arrays. In the case that the length "n" of a word is even, all nodes except for the control nodes may be combined. Since the array has an odd "n", the original nodes A, B and C exist in the lowest position(namely, most left position). It is possible to obtain an one-dimensional array(for example, bit-serial module multiplier) based on the mapping function. In the array, the most left node of each row generates a control signal. Each control node is formed of four gates(two XOR gates, one AND gate and one NOR gate) or two gates(one XOR gate and one NOR gate). The clock cycle of the array is determined by not the control nodes, but the process nodes.
Abstract translation: 目的：提供一种具有用于高速加密的阵列结构的模块化乘法装置，通过显着降低MSB的计算量来实现高速模乘法。 构成：每一行的两个节点组合为一个节点，并且数组之间保持规则性。 获得适用于VLSI的阵列结构。 节点X1，X2和X3是用于获得功能的节点。 节点AA，BB和CC是节点A，B和C由两个节点复制的节点。 节点组合实现线性结构和更容易的阵列硬件。 在单词的长度“n”为偶数的情况下，可以组合除了控制节点之外的所有节点。 由于阵列具有奇数“n”，原始节点A，B和C存在于最低位置（即最左侧位置）。 可以基于映射函数获得一维数组（例如，位串行模块乘法器）。 在阵列中，每行的最左边的节点产生一个控制信号。 每个控制节点由四个门（两个异或门，一个与门和一个或非门）或两个门（一个异或门和一个或非门）构成。 阵列的时钟周期由控制节点而不是进程节点决定。
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