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公开(公告)号：KR1020120036446A
公开(公告)日：2012-04-18
申请号：KR1020100098118
申请日：2010-10-08
Applicant: 삼성전자주식회사
CPC classification number: H05K1/0269 , H01L23/13 , H01L23/544 , H01L24/48 , H01L2223/54426 , H01L2223/54486 , H01L2224/4824 , H01L2224/73215 , H01L2224/92147 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H05K3/0052 , H05K2201/09936 , H05K2201/10159 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: PURPOSE: A printed circuit board for a board on chip package, the board on chip package including the same, and manufacturing methods thereof are provided to prevent a recognition error of a reject mark by including a reject marking unit on each unit substrate. CONSTITUTION: A base substrate(102) includes a circuit area(C) and a peripheral area(R). The base substrate includes a first surface(101a) and a second surface(101b). Circuit patterns(104c) are arranged in the circuit area. A reject marking unit(104r) is arranged in the peripheral area. An alignment mark is arranged in the edge of the peripheral area. A plating lead line is connected to the reject marking unit.
Abstract translation: 目的：一种用于片上封装的印刷电路板，包括其的片上封装及其制造方法，以通过在每个单元基板上包括拒绝标记单元来防止拒绝标记的识别错误。 构成：基底（102）包括电路区（C）和周边区（R）。 基底基板包括第一表面（101a）和第二表面（101b）。 电路图案（104c）布置在电路区域中。 拒收标记单元（104r）布置在周边区域中。 对准标记布置在周边区域的边缘。 电镀引线与废品标记单元连接。
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公开(公告)号：KR1020050077168A
公开(公告)日：2005-08-01
申请号：KR1020040005109
申请日：2004-01-27
Applicant: 삼성전자주식회사
CPC classification number: H01L2224/45144 , H01L2224/48227 , H01L2924/00
Abstract: 본 발명은 복수의 반도체 칩이 수직으로 적층되어 하나의 단위 반도체 칩 패키지로 구현되는 칩 스택 패키지와 그 제조 방법에 관한 것으로서, 종래 재배선 처리 과정이 요구되었던 칩 스택 패키지와 달리 제 1반도체 칩 상부 가장자리에서 본딩와이어의 일정 부분을 덮으며 소정 높이를 갖는 테두리 댐을 형성하고, 스크린 프린팅으로 테두리 댐의 내측의 본딩와이어 부분을 포함하여 상기 제 1반도체 칩 상부를 덮는 접착층을 형성하며, 접착층 상에 제 2반도체 칩이 부착되도록 함으로써, 재배선 처리 과정 없이 센터패드형의 반도체 칩을 적층하여 칩 스택 패키지를 구현할 수 있다. 테두리 댐과 접착층에 의해 본딩와이어가 보호되어 칩 스택 과정에서 와이어 손상이 방지될 수 있다. 그리고, 재배선 처리가 필요 없기 때문에 칩 스택 패키지의 제조 공정이 간단해지고 제조 비용이 감소될 수 있다.
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公开(公告)号：KR100833187B1
公开(公告)日：2008-05-28
申请号：KR1020060107943
申请日：2006-11-02
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L24/85 , H01L23/4952 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4846 , H01L2224/48471 , H01L2224/48475 , H01L2224/48479 , H01L2224/48599 , H01L2224/48644 , H01L2224/48699 , H01L2224/48744 , H01L2224/49111 , H01L2224/78301 , H01L2224/85051 , H01L2224/85205 , H01L2224/85444 , H01L2224/85986 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2224/85186 , H01L2924/00 , H01L2224/48227 , H01L2924/00015 , H01L2224/4554
Abstract: 루프 높이를 현저히 낮출 수 있으며, 결합 신뢰성이 향상되는 반도체 패키지의 와이어 본딩 방법이 개시된다. 본 발명의 와이어 본딩 방법은, 와이어를 공급할 수 있는 캐필러리를 사용하여 반도체 칩 상에 형성된 본딩 패드에 볼 범프를 형성한 후, 상기 캐필러리가 상기 볼 범프로부터 상기 와이어를 절단한다. 이어서 상기 캐필러리를 상기 반도체 칩의 본딩 패드와 대응하는 배선으로 이동하여 상기 배선 상에 상기 캐필러리로부터 공급되는 와이어를 스티치 본딩(stitch bonding)한다. 다시 상기 캐필러리를 상기 본딩 패드에 형성된 상기 볼 범프 위로 이동한 후 상기 볼 범프 상에 상기 와이어를 본딩한다.
루트, 패키지, 캐필러리, 본딩, 범프, 폴딩-
公开(公告)号：KR1020140069832A
公开(公告)日：2014-06-10
申请号：KR1020120137599
申请日：2012-11-30
Applicant: 삼성전자주식회사
CPC classification number: H01L24/75 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2221/68381 , H01L2224/131 , H01L2224/16225 , H01L2224/757 , H01L2224/759 , H01L2224/81024 , H01L2224/81815 , H01L2924/14 , H01L2924/014
Abstract: Disclosed is a device for mounting a semiconductor chip. The device for mounting a semiconductor chip includes a coating part for coating a solder bump of a semiconductor chip with flux. The coating part comprises a coating tank which is filled with flux and into which the solder bump is dipped; and a flux tank for supplying flux to the coating tank. A sensor automatically measures a flux level inside the flux tank to automatically fill the flux tank with flux when the measured flux level is lower than a predetermined level. Thus, the present invention can prevent poor flux coating on the solder bump, caused by a flux shortage in the coating tank.
Abstract translation: 公开了一种用于安装半导体芯片的装置。 用于安装半导体芯片的装置包括用于通过焊剂涂覆半导体芯片的焊料凸点的涂覆部分。 涂层部分包括填充有焊剂的涂层槽，焊料凸块浸入其中; 以及用于向涂料槽供给助熔剂的助熔剂罐。 当测量的磁通水平低于预定水平时，传感器自动测量磁通罐内的通量水平，以自动填充磁通槽。 因此，本发明可以防止由于涂料槽中的焊剂不足而引起的焊料凸块上的焊剂不良。
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Patent Agency Ranking
公开(公告)号：KR1020130030370A
公开(公告)日：2013-03-27
申请号：KR1020110093788
申请日：2011-09-19
Applicant: 삼성전자주식회사
CPC classification number: H01L24/14 , H01L23/49816 , H01L23/49838 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L2224/0401 , H01L2224/06102 , H01L2224/13099 , H01L2224/1403 , H01L2224/141 , H01L2224/14515 , H01L2224/16237 , H01L2224/17104 , H01L2224/17517 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2924/00 , H01L23/48 , H01L23/12 , H01L23/488
Abstract: PURPOSE: A package substrate and a semiconductor package including the same are provided to improve electrical connection reliability by securing an accurate contact between a signal bump and a signal pad. CONSTITUTION: A semiconductor chip is located on the upper side of an insulation substrate(110) by using a signal bump and a dummy bump with the same thicknesses. A dummy pad(124) is formed on the upper side of the insulation substrate and is connected to the dummy bump. A signal pad is formed on the upper side of the insulation substrate and is connected to the signal bump. A plug(130) is composed of a top part and a bottom part. The top part is exposed through the upper side of the insulation substrate and is connected to the signal pad and the dummy pad. The bottom part is exposed through the lower side of the insulation substrate.
Abstract translation: 目的：提供封装基板和包括该封装基板的半导体封装以通过确保信号凸块与信号垫之间的精确接触来提高电连接的可靠性。 构成：通过使用具有相同厚度的信号凸块和虚拟凸块，半导体芯片位于绝缘基板（110）的上侧。 在绝缘基板的上侧形成有虚拟焊盘（124），并与虚设凸块连接。 信号焊盘形成在绝缘基板的上侧并连接到信号凸块。 插头（130）由顶部和底部组成。 顶部通过绝缘基板的上侧露出，并连接到信号垫和虚拟垫。 底部通过绝缘基板的下侧露出。
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公开(公告)号：KR1020070080324A
公开(公告)日：2007-08-10
申请号：KR1020060011539
申请日：2006-02-07
Applicant: 삼성전자주식회사
IPC: H01L23/28
CPC classification number: H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/4826 , H01L2224/73215 , H01L2224/73265 , H01L2224/92147 , H01L2924/15311 , H01L2924/181 , H01L24/26 , H01L21/0231 , H01L21/78 , H01L25/074 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
Abstract: A method for attaching and stacking a semiconductor chip using a polyimide layer is provided to simplify an attachment process and a stacking process by attaching the semiconductor chip on a package substrate or stacking the semiconductor chip to another semiconductor chip. A supplying process is performed to supply a wafer(110). The wafer includes a plurality of semiconductor chips. The semiconductor chips are arranged on an upper surface of the wafer. A polyimide layer with adhesive strength is formed on each of the semiconductor chips. The semiconductor chips are separated from each other by cutting the wafer(120). A package substrate preparation process is performed to prepare a package substrate(130). The semiconductor chips are mounted on the package substrate. The semiconductor chips are attached through the polyimide layer onto the package substrate(140). The polyimide layer is cured(150).
Abstract translation: 提供一种使用聚酰亚胺层附着和堆叠半导体芯片的方法，以通过将半导体芯片附着在封装基板上或将半导体芯片堆叠到另一半导体芯片来简化附接处理和堆叠处理。 执行供给处理以提供晶片（110）。 晶片包括多个半导体芯片。 半导体芯片布置在晶片的上表面上。 在每个半导体芯片上形成具有粘合强度的聚酰亚胺层。 半导体芯片通过切割晶片（120）而彼此分离。 执行封装衬底制备工艺以制备封装衬底（130）。 半导体芯片安装在封装基板上。 半导体芯片通过聚酰亚胺层附着到封装衬底（140）上。 聚酰亚胺层被固化（150）。
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公开(公告)号：KR101896972B1
公开(公告)日：2018-09-11
申请号：KR1020110093788
申请日：2011-09-19
Applicant: 삼성전자주식회사
CPC classification number: H01L24/14 , H01L23/49816 , H01L23/49838 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L2224/0401 , H01L2224/06102 , H01L2224/13099 , H01L2224/1403 , H01L2224/141 , H01L2224/14515 , H01L2224/16237 , H01L2224/17104 , H01L2224/17517 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
Abstract: 패키지기판은절연기판, 더미패드, 신호패드및 플러그를포함한다. 절연기판의상부면에는동일한두께를갖는신호범프와더미범프를매개로반도체칩이안치된다. 더미패드는상기절연기판의상부면에형성되어, 상기더미범프와연결된다. 신호패드는상기절연기판의상부면에형성되어상기신호범프와연결된다. 신호패드는상기더미패드의상부면보다돌출된상부면을갖는다. 플러그는상기절연기판의상부면을통해서노출되어상기신호패드와상기더미패드와연결된상단, 및상기절연기판의하부면을통해서노출된하단을갖는다. 따라서, 상기된패키지기판을갖는반도체패키지는강한결합력을가지면서향상된전기적연결신뢰성을갖게된다.
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公开(公告)号：KR1020080040246A
公开(公告)日：2008-05-08
申请号：KR1020060107943
申请日：2006-11-02
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L24/85 , H01L23/4952 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4846 , H01L2224/48471 , H01L2224/48475 , H01L2224/48479 , H01L2224/48599 , H01L2224/48644 , H01L2224/48699 , H01L2224/48744 , H01L2224/49111 , H01L2224/78301 , H01L2224/85051 , H01L2224/85205 , H01L2224/85444 , H01L2224/85986 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2224/85186 , H01L2924/00 , H01L2224/48227 , H01L2924/00015 , H01L2224/4554
Abstract: A wire bonding method for a semiconductor package is provided to form a thin semiconductor package by performing a stitch bonding process without forming a loop height on a bonding pad. A ball bump(118) is formed on a bonding pad(116) formed on a semiconductor chip(112) by using a capillary(120) capable of supplying a wire(122). The wire is cut from the ball bump by the capillary. The capillary is transferred to an interconnection corresponding to the bonding pad on the semiconductor chip to perform a stitch bonding process on the wire supplied from the capillary so that the wire is stitched to the interconnection. After the capillary is transferred over the ball bump formed on the bonding pad, the wire is bonded to the surface of the ball bump by a stitch bonding process. The wire is cut from the ball bump.
Abstract translation: 提供一种用于半导体封装的引线接合方法，通过在接合焊盘上形成环路高度进行缝合接合工艺来形成薄的半导体封装。 通过使用能够供应导线（122）的毛细管（120），在形成在半导体芯片（112）上的焊盘（116）上形成球凸点（118）。 电线通过毛细管从球凸块切割。 将毛细管转移到与半导体芯片上的接合焊盘相对应的互连件上，以对从毛细管供给的导线进行针脚接合处理，从而将线缝合到互连。 在将毛细管转移到形成在焊盘上的球凸起之后，通过缝合接合工艺将导线接合到球凸块的表面。 电线从球凸块切割。
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10.发明公开범프 리버스 스티치 본딩 방법, 그를 이용한 칩 적층구조와 칩 적층 방법 无效BUMP REVERSE STITCH BONDING METHOD，CHIP STACK STRUCTURE AND METHOD WITH THE SAME
公开(公告)号：KR1020070062084A
公开(公告)日：2007-06-15
申请号：KR1020050121790
申请日：2005-12-12
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48472 , H01L2224/48479 , H01L2224/73265 , H01L2224/78301 , H01L2224/85 , H01L2224/85051 , H01L2224/85186 , H01L2224/85986 , H01L2224/92247 , H01L2924/00014 , H01L2924/01082 , H01L2924/00012 , H01L2924/00 , H01L2224/4554
Abstract: A bump reverse stitch bonding method, a chip stacked structure using the same and a chip stacking method are provided to secure the reliability of bonding between a lead of a circuit board and a bonding wire and to prevent generation of short between adjacent bonding wires. A circuit board(110) is provided. A semiconductor chip with chip pads is mounted on the circuit board. The circuit board has a lead adjacent to the chip. A ball bump(152) is formed on the chip pad of the chip by using a capillary loaded with a bonding wire. The capillary cuts the bonding wire at the ball bump. A bonding wire(154) is drawn as much as a predetermined length from the capillary downward. A first bonding portion is formed on the lead of the circuit board by performing a first stitch bonding process using the capillary. A wire loop portion(150) is formed from the first bonding portion to the ball bump of the chip by raising vertically the bonding wire as much as the chip height or more and moving the bonding wire. A second bonding portion(158) is formed on the ball bump of the chip by performing a second stitch bonding process using the capillary. The capillary cuts the bonding wire at the second bonding portion.
Abstract translation: 提供凸起反向针迹接合方法，使用其的芯片堆叠结构和芯片堆叠方法以确保电路板的引线和接合线之间的接合的可靠性，并且防止相邻接合线之间的短路。 提供电路板（110）。 具有芯片焊盘的半导体芯片安装在电路板上。 电路板具有与芯片相邻的引线。 通过使用装有接合线的毛细管在芯片的芯片焊盘上形成球凸块（152）。 毛细管切割球凸点处的接合线。 接合线（154）从毛细管向下拉出预定长度。 通过使用毛细管进行第一针迹接合处理，在电路板的引线上形成第一接合部。 通过将接合线垂直地升高到芯片高度或更高，并且移动接合线，从芯片的第一接合部分到芯片的球凸块形成线环部分（150）。 通过使用毛细管进行第二针迹接合处理，在芯片的球凸部上形成第二接合部（158）。 毛细管在第二接合部分切割接合线。
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