公开(公告)号：KR1020080056795A

公开(公告)日：2008-06-24

申请号：KR1020060129779

申请日：2006-12-19

Applicant: 삼성전자주식회사

Inventor： 김영승 ,  박철성 ,  유병욱

IPC: G11C29/00 ,  G11C8/12

Abstract: A memory device and a method for testing the memory device are provided to perform static burn-in mode, dynamic burn-in mode and scan mode in a wafer burn-in step. A memory device comprises a memory block(400) and a number of input pins(100) to receive a number of mode selection signals. A test mode selection block(200) enables one of a number of mode signals on the basis of the mode selection signals and then outputs the enabled mode signal. A pattern generation block(300) generates a burn-in clock signal, an address and a test pattern in response to a received mode signal. A test pattern comparison block(500) compares the test pattern outputted from the memory block with a test pattern read out from the memory block, and then outputs comparison result. An output pin(600) outputs the comparison result to a host.

Abstract translation: 提供了一种用于测试存储器件的存储器件和方法，用于在晶片老化步骤中执行静态老化模式，动态老化模式和扫描模式。 存储器件包括存储块（400）和多个输入引脚（100），用于接收多个模式选择信号。 测试模式选择块（200）基于模式选择信号启用多个模式信号中的一个，然后输出使能模式信号。 模式生成块（300）响应于接收的模式信号产生老化时钟信号，地址和测试模式。 测试图案比较块（500）将从存储块输出的测试图案与从存储器块读出的测试图案进行比较，然后输出比较结果。 输出引脚（600）将比较结果输出到主机。

公开(公告)号：KR101941685B1

公开(公告)日：2019-01-23

申请号：KR1020180122629

申请日：2018-10-15

Applicant: 삼성전자주식회사

Inventor： 정종원 ,  이지열 ,  박정일 ,  유병욱 ,  이상윤 ,  진용완

IPC: H01L51/05 ,  H01L51/00 ,  H01L51/10

公开(公告)号：KR101778223B1

公开(公告)日：2017-09-15

申请号：KR1020080090007

申请日：2008-09-11

Applicant: 삼성전자주식회사

Inventor： 박경배 ,  류명관 ,  유병욱 ,  이상윤 ,  김태상 ,  권장연 ,  손경석 ,  정지심

IPC: G02F1/136 ,  H01L29/786

CPC classification number: H01L29/78609 ,  H01L29/78618

Abstract: 박막트랜지스터가개시된다. 개시된박막트랜지스터는, 채널과소스및 드레인사이에형성된중간층을포함함으로써, 박막트랜지스터에서발생할수 있는드레인영역의높은오프전류를감소시켜안정된구동이가능한박막트랜지스터를제공한다.

公开(公告)号：KR101512818B1

公开(公告)日：2015-05-20

申请号：KR1020080099608

申请日：2008-10-10

Applicant: 삼성전자주식회사

Inventor： 손경석 ,  김태상 ,  권장연 ,  정지심 ,  이상윤 ,  류명관 ,  박경배 ,  유병욱

IPC: H01L29/786

Abstract: 개시된산화물반도체트랜지스터는산화물반도체로이루어진채널층과제1 게이트사이에형성되는제1 게이트절연막; 및채널층과제2 게이트사이에형성되는제2 게이트절연막;을포함하며, 상기제1 게이트절연막및 제2 게이트절연막은서로다른물질로이루어진다.

公开(公告)号：KR1020120082699A

公开(公告)日：2012-07-24

申请号：KR1020110004137

申请日：2011-01-14

Applicant: 삼성전자주식회사

Inventor： 유병욱 ,  박정일 ,  진용완 ,  이상윤 ,  구본원 ,  정종원

IPC: H01L51/05 ,  H01L51/00 ,  C07D249/18 ,  C07D277/62 ,  C07D471/04

CPC classification number: H01L51/0508 ,  C07D249/18 ,  C07D277/62 ,  C07D471/04 ,  H01L51/0072 ,  H01L51/0545

Abstract: PURPOSE: An organic thin film transistor, method of manufacturing the same and electronic device are provided to prevent oxidation or corrosion of an electrode by putting a self-assembled monolayer on an interface of an organic semiconductor layer and a source and a drain electrodes. CONSTITUTION: A gate electrode(12) is formed on a substrate(11). A gate insulating substrate is formed on the substrate including the gate electrode. A source(16) and drain(17) electrodes including an organic semiconductor layer(15) are formed on the gate substrate. A self-assembled monolayer(14) is formed on an interface between the electrodes of the source and drain and organic semiconductor layer.

Abstract translation: 目的：提供一种有机薄膜晶体管及其制造方法和电子器件，以通过将自组装单层置于有机半导体层和源极和漏极的界面上来防止电极的氧化或腐蚀。 构成：在基板（11）上形成栅电极（12）。 在包括栅电极的基板上形成栅绝缘基板。 在栅极衬底上形成包括有机半导体层（15）的源极（16）和漏极（17）。 在源极和漏极和有机半导体层的电极之间的界面上形成自组装单层（14）。

公开(公告)号：KR1020100008210A

公开(公告)日：2010-01-25

申请号：KR1020080068664

申请日：2008-07-15

Applicant: 삼성전자주식회사

Inventor： 류명관 ,  박경배 ,  이상윤 ,  권장연 ,  유병욱 ,  김태상 ,  손경석 ,  정지심

IPC: H01L29/786

CPC classification number: H01L29/78624 ,  H01L29/66765 ,  H01L29/458 ,  H01L29/78621

Abstract: PURPOSE: A poly-Si thin film transistor and method of manufacturing the same are provided to reduce the cost without the additional ion injection processes and photolithographic process. CONSTITUTION: In order that the gate(112) is covered, the gate insulating layer(114) is formed in the top of the substrate. The active layer(116) is formed on the gate insulating layer. The active layer is composed of the poly-silicon. The first polysilicon layer(117) is respectively formed in both-sided upper side of the active layer. The first polysilicon layer is doped in the low concentration. The second polysilicon layer(118) is respectively formed in the upper side of first polysilicon layers. The second polysilicon layer is doped in the concentration like the first polysilicon layer or the high concentration. Source / drain electrodes(120a,120b) are respectively formed in the upper side of second polysilicon layers.

Abstract translation: 目的：提供多晶硅薄膜晶体管及其制造方法，以降低成本，而不需要额外的离子注入工艺和光刻工艺。 构成：为了使栅极（112）被覆盖，栅极绝缘层（114）形成在衬底的顶部。 有源层（116）形成在栅极绝缘层上。 有源层由多晶硅组成。 第一多晶硅层（117）分别形成在有源层的双面上侧。 第一多晶硅层以低浓度掺杂。 第二多晶硅层（118）分别形成在第一多晶硅层的上侧。 第二多晶硅层以类似于第一多晶硅层或高浓度的浓度掺杂。 源极/漏极（120a，120b）分别形成在第二多晶硅层的上侧。