公开(公告)号：KR1020130118708A

公开(公告)日：2013-10-30

申请号：KR1020120059143

申请日：2012-06-01

Applicant: 조선대학교산학협력단

Inventor： 이정아 ,  하산베이그

IPC: H03K19/173 ,  G06F11/07

Abstract: PURPOSE: A fault-tolerant field programmable gate array (FPGA) of a self-healing bio-simulation type is provided to normally operate a corresponding computation cell and a corresponding computation tile by outputting a normal output signal even when a temporary error or a permanent error occurs in the computation cell. CONSTITUTION: A plurality of computation units receives first and second functions and compares a stored error correction code and a generated error detection code signal to detect an internal temporary or permanence error. At least one stem cell (20) is connected to the computation unit, replaces the function of a computation unit in which a permanence error occurs, and is partially restructured. A computation block (50) connects each stem cell and the plurality of computation units in a row. A plurality of computation tiles comprises the plurality of computation blocks which is arranged in a horizontal or vertical direction. When a permanent error occurs in at least two computation tiles of the computation tiles, a fault-tolerant core controls sets up the priority of the computation tiles from which the permanent error is detected to control the healing of the permanent error according to the priority.

Abstract translation: 目的：提供自修复生物模拟类型的容错现场可编程门阵列（FPGA），以便即使在临时错误或永久性的时候也输出正常的输出信号来正常操作相应的计算单元和相应的计算块 在计算单元中出现错误。 构成：多个计算单元接收第一和第二功能，并比较存储的纠错码和产生的错误检测码信号，以检测内部临时或永久性错误。 至少一个干细胞（20）连接到计算单元，代替发生持久性错误并被部分重构的计算单元的功能。 计算块（50）连接每个干细胞和多个计算单元。 多个计算瓦片包括沿水平或垂直方向布置的多个计算块。 当在计算瓦片的至少两个计算瓦片中发生永久性错误时，容错核心控制器设置检测到永久错误的计算瓦片的优先级，以根据优先级控制永久错误的愈合。

公开(公告)号：KR101268998B1

公开(公告)日：2013-05-29

申请号：KR1020120006065

申请日：2012-01-19

Applicant: 조선대학교산학협력단

Inventor： 이정아 ,  소마순다람,나타르잔

IPC: G06F11/10

Abstract: PURPOSE: An error detection device based on scalable error detection coding for a programmable shift/rotate operation unit and a self-checking programmable shift/rotate operation unit which includes the error detection device are provided to generate and compare linear flexible SEDC for input various bits, thereby detecting errors in a shift/rotate operation. CONSTITUTION: An input SEDC generator(110) receives binary input data and a shift bit and generates input SEDC corresponding to kinds of a shift/rotate operation. An error detector(120) receives binary output data and an input error detection code and generates output SEDC. The error detector outputs an error detection result by determining identity of the output SEDC and the input SEDC. An input error detection code generator includes a 2 bit SEDC truth table, which stores 2 bit SEDC, and an input SEDC generation unit which generates the input SEDC.

Abstract translation: 目的：提供一种基于可编程移位/旋转操作单元的可伸缩错误检测编码的错误检测装置和包括错误检测装置的自检可编程移位/旋转操作单元，用于生成和比较用于输入各种位的线性灵活SEDC ，从而检测换档/旋转操作中的错误。 构成：输入SEDC发生器（110）接收二进制输入数据和移位位，并产生对应于移位/旋转操作的种类的输入SEDC。 误差检测器（120）接收二进制输出数据和输入错误检测码并产生输出SEDC。 误差检测器通过确定输出SEDC和输入SEDC的标识来输出错误检测结果。 输入错误检测码发生器包括存储2位SEDC的2位SEDC真值表和生成输入SEDC的输入SEDC生成单元。

公开(公告)号：KR101268997B1

公开(公告)日：2013-05-29

申请号：KR1020120002924

申请日：2012-01-10

Applicant: 조선대학교산학협력단

Inventor： 이정아 ,  소마순다람,나타르잔

IPC: G06F11/26 ,  G06F11/10

Abstract: PURPOSE: An error detection device based on SEDC(Scalable Error Detection Coding) for a programmable Boolean operation unit and a self-checking programmable Boolean operation unit which includes the error detection device are provided to separately perform generation of SEDC from input data, thereby implementing a combination approval system without decreasing speed of a Boolean operation or deteriorating performance of latency. CONSTITUTION: An input SEDC generator(110) receives binary input data and generates input SEDC corresponding to kinds of a Boolean operation. An error detector(120) receives the binary output data and the input SEDC and generates output SEDC. The error detector outputs an error detection result by determining identity of the output SEDC and the input SEDC. The input SEDC generator includes a 2 bit input SEDC generation unit which generates the 2 bit input SEDC as the input SEDC.

Abstract translation: 目的：提供一种基于用于可编程布尔运算单元的SEDC（可伸缩误差检测编码）和包括错误检测装置的自检可编程布尔运算单元的错误检测装置，以分别从输入数据执行SEDC的生成，从而实现 组合审批系统，而不会降低布尔运算速度或降低延迟性能。 构成：输入SEDC发生器（110）接收二进制输入数据并生成与布尔运算种类对应的输入SEDC。 误差检测器（120）接收二进制输出数据和输入SEDC并产生输出SEDC。 误差检测器通过确定输出SEDC和输入SEDC的标识来输出错误检测结果。 输入SEDC发生器包括2位输入SEDC生成单元，其生成作为输入SEDC的2位输入SEDC。

公开(公告)号：KR101267894B1

公开(公告)日：2013-05-27

申请号：KR1020110098730

申请日：2011-09-29

Applicant: 조선대학교산학협력단

Inventor： 이정아 ,  소마순다람,나타르잔 ,  이정근

IPC: G06F11/10

Abstract: 본발명은확장형오류검출코드생성기, 그생성기를구비한자가검사룩업테이블및 확장형오류검출코드생성방법에관한것으로, 보다구체적으로는서로다른길이의이진입력데이터에대해오류검출코드를생성하는복수개의오류검출코드생성수단을구비하여, 상기오류검출코드생성수단들단독또는조합에의해오류검출코드의길이를유동적으로확장할수 있어, 최소한의하드웨어추가로이진입력데이터전체의단방향오류를검출할수 있는확장형오류검출코드생성기와오류검출코드생성방법그리고상기확장형오류검출코드생성기를구비하여 LUT데이터전체를자가검사하거나매 동작시 LUT데이터를자가검사할수 있는자가검사룩업테이블에관한것이다.

公开(公告)号：KR1020130034713A

公开(公告)日：2013-04-08

申请号：KR1020110098730

申请日：2011-09-29

Applicant: 조선대학교산학협력단

Inventor： 이정아 ,  소마순다람,나타르잔 ,  이정근

IPC: G06F11/10

Abstract: PURPOSE: An SEDC(Scalable Error Detection Coding) generator, a lookup table including the SEDC generator, and an SEDC generation method are provided to generate SEDC for a lookup table data of in a length direction, thereby performing a unidirectional error check for the entire lookup table data. CONSTITUTION: A code length calculation module calculates the length of SEDC which is generated for binary input data. An SEDC generation module(100) includes a 2 bit input SEDC generation unit(110), a 3 bit input SEDC generation unit(120), or a 4 bit input SEDC generation unit. The SEDC generation module generates SEDC of a calculated length by an individual or a combination of the SEDC generation units.

Abstract translation: 目的：提供SEDC（可伸缩错误检测编码）生成器，包括SEDC生成器的查找表和SEDC生成方法，以生成用于长度方向的查找表数据的SEDC，从而对整个步骤执行单向错误检查 查找表数据。 构成：代码长度计算模块计算为二进制输入数据生成的SEDC的长度。 SEDC生成模块（100）包括2位输入SEDC生成单元（110），3位输入SEDC生成单元（120）或4位输入SEDC生成单元。 SEDC生成模块通过个体或SEDC生成单元的组合生成计算出的长度的SEDC。

公开(公告)号：KR102134315B1

公开(公告)日：2020-07-16

申请号：KR1020180158929

申请日：2018-12-11

Applicant: 조선대학교산학협력단

Inventor： 이정아 ,  인야앳울라 ,  자히드울라

IPC: G11C15/04

公开(公告)号：KR101981694B1

公开(公告)日：2019-05-23

申请号：KR1020170167571

申请日：2017-12-07

Applicant: 조선대학교산학협력단

Inventor： 이정아 ,  아프잘우마

IPC: H03K19/177 ,  G06F17/50

公开(公告)号：KR101899065B1

公开(公告)日：2018-09-14

申请号：KR1020160135758

申请日：2016-10-19

Applicant: 조선대학교산학협력단

Inventor： 이정아 ,  아리핀투바 ,  하싼압두스사미 ,  호세인무라디안사드로우디

IPC: G06F7/501

Abstract: 본발명은정확한전가산기회로및 디지털신호처리장치에관한것으로, 보다구체적으로는 18개의트랜지스터만으로에러가없는정확한캐리아웃신호및 합신호를출력할수 있는정확한전가산기회로및 그전가산기회로가집적된디지털신호처리장치에관한것이다.

公开(公告)号：KR101882349B1

公开(公告)日：2018-08-24

申请号：KR1020160130770

申请日：2016-10-10

Applicant: 조선대학교산학협력단

Inventor： 이정아 ,  인야앳울라 ,  자히드울라

IPC: G06F12/02

CPC classification number: Y02D10/13

Abstract: 본발명은 SRAM 기반의 TCAM 주소맵핑방법및 TCAM 주소생성장치에관한것으로, 보다구체적으로는메모리나전력소모의증가없이해당 TCAM 데이터가저장된주소를빠르게출력할수 있게하는 SRAM 기반의 TCAM 주소맵핑방법및 TCAM 주소생성장치에관한것이다.

公开(公告)号：KR101596422B1

公开(公告)日：2016-03-07

申请号：KR1020140032679

申请日：2014-03-20

Applicant: 조선대학교산학협력단

Inventor： 이정아 ,  최광진 ,  한승협 ,  신상우

IPC: H04W4/02 ,  H04W64/00 ,  H04W88/02

Abstract: 본발명은미디어볼륨제어프로그램이저장된컴퓨터로읽을수 있는기록매체, 그프로그램이설치된스마트기기, 웹어플리케이션서버, 데이터베이스서버, 미디어볼륨제어시스템및 방법에관한것으로, 보다구체적으로는미디어프로그램이실행되고있는스마트기기가위험지역으로진입할때, 미디어프로그램의볼륨을낮춰보행자의안전보행을도모할수 있게한 미디어볼륨제어프로그램이저장된컴퓨터로읽을수 있는기록매체, 그프로그램이설치된스마트기기, 웹어플리케이션서버, 데이터베이스서버, 미디어볼륨제어시스템및 방법에관한것이다.