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公开(公告)号：KR101483739B1
公开(公告)日：2015-02-04
申请号：KR1020130105983
申请日：2013-09-04
Applicant: 한국과학기술원
IPC: H03F3/217
CPC classification number: H03F3/2176 , H03F1/0277 , H03F1/42 , H03F1/56 , H03F3/602 , H03F2200/541 , H03F2200/543
Abstract: 본 발명은 입력 디퍼렌셜 신호를 증폭시키는 복수의 차동증폭기 및 상기 차동증폭기의 출력을 출력단에 전달하는 전압결합 전송선 트랜스포머를 포함하되, 사용 주파수에 따라 상기 전송선 트랜스포머에 DC 전원이 공급되는 위치를 가변시킴으로써 주파수 특성이 가변되는 것을 특징으로 하는 다중대역 E급 전력증폭기에 관한 것이다.
Abstract translation: 本发明涉及一种包括放大输入差分信号的多个差分放大器的多频带E类功率放大器和将差分放大器的输出传送到输出端子的电压组合传输线变压器。 本发明通过根据使用频率改变向传输线变压器提供DC功率的位置来改变频率的性质。
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公开(公告)号：KR1020100003422A
公开(公告)日：2010-01-11
申请号：KR1020080063306
申请日：2008-07-01
Applicant: 한국과학기술원
IPC: H01L29/41
Abstract: PURPOSE: A passive matrix-addressable memory device is provided to maintain data state stored at a memory cell by reducing a size of an interference voltage applied to a memory unit. CONSTITUTION: One parallel second electrode line(220) or more are formed to a cross direction with a first electrode line(210). A memory unit(100) is formed between the first and second electrode lines and includes electrically polarizable material showing hysteresis. A switch is formed between the memory unit and the first electrode line. The switch unit has increased current conductivity when the applied voltage is above a threshold voltage. A depolarization preventing unit is formed between the switch unit and the memory unit and prevents the depolarization on the interface between the switch unit and the memory. The depolarization preventing unit includes a metal material or electrical conductive polymer material.
Abstract translation: 目的：提供无源矩阵寻址存储器件，通过减小施加到存储器单元的干扰电压的大小来保持存储在存储器单元中的数据状态。 构成：在与第一电极线（210）的交叉方向上形成一个平行的第二电极线（220）或更多。 存储单元（100）形成在第一和第二电极线之间，并且包括显示滞后的电极化材料。 在存储单元和第一电极线之间形成开关。 当施加的电压高于阈值电压时，开关单元具有增加的电流传导性。 在开关单元和存储单元之间形成去极化防止单元，并防止开关单元和存储器之间的接口上的去极化。 去极化防止单元包括金属材料或导电聚合物材料。
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公开(公告)号：KR101839903B1
公开(公告)日：2018-03-19
申请号：KR1020160062880
申请日：2016-05-23
Applicant: 한국과학기술원
IPC: H01L21/033 , G03F7/029 , H01L21/027 , H01L21/56 , H01L21/02
Abstract: 본발명의실시형태에따른메타물질을갖는마스크형성방법은, 자외선투과기판상에자외선차단막을형성하는단계; 상기자외선차단막을패터닝하여패터닝된자외선차단막과상기자외선투과기판을포함하는마스크를형성하는단계; 메타물질을미리준비하는단계; 및상기마스크에상기메타물질을전사하는단계;를포함한다. 이러한메타물질을갖는마스크형성방법에의하면, 마스크의표면구조에관계없이메타물질의형태를그대로유지시키면서마스크로전사할수 있어마스크에전사된메타물질의광 특성이변하지않는이점이있다.
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公开(公告)号：KR101810406B1
公开(公告)日：2017-12-20
申请号：KR1020160033595
申请日：2016-03-21
Applicant: 한국과학기술원
IPC: H01L45/00
CPC classification number: H01L45/00
Abstract: 본발명에따른메모리소자는, 기판, 기판상에위치하고전기전도성을가지는결합층, 상기결합층의상부또는하부에위치하는메타원자층, 메타원자층상부에위치하는메모리층및 메모리층상에위치하고전기전도성을가지는전극층을포함하며, 메모리층은소정전압이상에서자발분극을형성하는물질로구성된다. 이에의하여, 전기적으로구동가능하고, 변조된광특성을지속적으로유지할수 있게된다. 또한, 본발명에따른메모리소자는다중전기적입력에의한광특성변조가가능해진다.
Abstract translation: 根据本发明的存储器件包括衬底，位于衬底上的具有导电性的耦合层，位于耦合层上方或下方的元原子层，位于元原子层上方的存储层， 并且存储层由在预定电压或更高电压下形成自发极化的材料制成。 这使得可以连续地和电地维持调制的光学特性。 另外，根据本发明的存储装置能够通过多个电输入来调制光的特性。
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Patent Agency Ranking
公开(公告)号：KR1020170109447A
公开(公告)日：2017-09-29
申请号：KR1020160033595
申请日：2016-03-21
Applicant: 한국과학기술원
IPC: H01L45/00
CPC classification number: H01L45/00
Abstract: 본발명에따른메모리소자는, 기판, 기판상에위치하고전기전도성을가지는결합층, 상기결합층의상부또는하부에위치하는메타원자층, 메타원자층상부에위치하는메모리층및 메모리층상에위치하고전기전도성을가지는전극층을포함하며, 메모리층은소정전압이상에서자발분극을형성하는물질로구성된다. 이에의하여, 전기적으로구동가능하고, 변조된광특성을지속적으로유지할수 있게된다. 또한, 본발명에따른메모리소자는다중전기적입력에의한광특성변조가가능해진다.
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公开(公告)号：KR1020150039240A
公开(公告)日：2015-04-10
申请号：KR1020130117154
申请日：2013-10-01
Applicant: 한국과학기술원
IPC: H03F1/32
CPC classification number: H03F1/0222 , H03F3/193 , H03F3/2173 , H03F3/245 , H03F3/45183 , H03F3/45188 , H03F3/45475 , H03F3/604 , H03F2200/102 , H03F2200/432 , H03F2200/451 , H03F2203/45302 , H03F2203/45731
Abstract: 본발명은제1 포락선전압(Venv1)의변동에따라비례하여증폭된전원전압을생성하는포락선증폭기, 상기제1 포락선전압(Venv1)이스케일링된제2 포락선전압(Venv2)의변동에따라비례하여증폭시키는공통게이트전원변조선형화기및 상기포락선증폭기의출력을전원전압및 드레인바이어스로입력받고상기공통게이트전원변조선형화기의출력을공통게이트바이어스로입력받아, 포락선에따라출력커패시턴스를일정하게유지시켜 RF 신호를증폭하는전력증폭기를포함하는것을특징으로하는공통게이트전압변조선형화기를이용한포락선추적전력송신기에관한발명이다.
Abstract translation: 本发明涉及使用共栅极电压调制线性化电路的包络跟踪功率发射器。 产生与第一包络电压（Venv1）的变化成比例地放大的电压的包络放大器，与第二包络电压（Venv2）的变化成比例地放大的公共栅极功率调制线性化电路， 电压（Venv1）和功率放大器，其接收具有电源电压和漏极偏置的包络放大器的输出，并接收共栅极电压调制线性化电路的输出，并具有公共栅极偏置，并放大保持输出电容的RF信号 根据信封。
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公开(公告)号：KR101429160B1
公开(公告)日：2014-09-23
申请号：KR1020130071575
申请日：2013-06-21
Applicant: 한국과학기술원
IPC: H01L27/115 , H01L21/8247
CPC classification number: G11C11/5657 , G11C11/56 , G11C13/025 , H01L21/28273 , B82Y10/00 , G11C11/22 , H01L21/28291
Abstract: An embodiment of the present invention relates to a multi-bit memory element. According to the embodiment of the present invention, the memory element includes: a substrate; a first electrode placed on the substrate; a first memory part placed on the substrate and the first electrode containing an electrically polarizing material indicating hysteresis; a semiconductor part placed on the first memory part; a source electrode placed on a side of the semiconductor part; a drain electrode placed on the other side of the semiconductor part; a second memory part placed on the semiconductor part, placed between the source electrode and the drain electrode containing the electrically polarizing material indicating hysteresis; and a second electrode placed on the second memory part. When a first operating voltage is applied to the first electrode and a second operating voltage is not applied to the second electrode, a current I_D1 flows in the semiconductor part. When the first operating voltage is not applied to the first electrode and the second operating voltage is applied to the second electrode, a current I_D2 flows in the semiconductor part. When the first operating voltage is applied to the first electrode and the second operating voltage is applied to the second electrode, a current I_D3 (I_D1+I_D2) flows in the semiconductor part and the current I_D1 is larger than the current I_D2.
Abstract translation: 本发明的实施例涉及一种多位存储元件。 根据本发明的实施例，存储元件包括：基板; 放置在基板上的第一电极; 放置在基板上的第一存储器部分和包含表示磁滞的电极化材料的第一电极; 放置在第一存储器部分上的半导体部件; 位于所述半导体部件侧的源电极; 放置在所述半导体部件的另一侧的漏电极; 放置在半导体部分上的第二存储器部分，放置在包含指示滞后的电极化材料的源电极和漏电极之间; 以及放置在第二存储器部分上的第二电极。 当向第一电极施加第一工作电压并且第二工作电压不施加到第二电极时，电流I_D1在半导体部件中流动。 当第一工作电压不施加到第一电极并且第二工作电压施加到第二电极时，电流I_D2流入半导体部件。 当第一工作电压被施加到第一电极并且第二工作电压被施加到第二电极时，电流I_D3（I_D1 + I_D2）在半导体部分中流动，并且电流I_D1大于当前I_D2。
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公开(公告)号：KR1020130097502A
公开(公告)日：2013-09-03
申请号：KR1020120019211
申请日：2012-02-24
Applicant: 한국과학기술원
CPC classification number: H03F3/16 , G06F17/5072 , H03F1/0227
Abstract: PURPOSE: An efficiency-improved envelope amplifier using a dual switching amplifier and a designing method thereof are provided to reduce power consumption, thereby improving efficiency compared with an existing envelope amplifier. CONSTITUTION: An efficiency-improved envelope amplifier includes a linear amplifier (1) and a switching amplifier (2). The switching amplifier includes at least two switching stages (21,22) which are selectively actuated by the size of an envelope input signal. The switching stage comprises a p-channel metal-oxide semiconductor (PMOS) and an n-channel metal oxide semiconductor (NMOS). The envelop amplifier has a structure in which the linearity of the linear amplifier and the high efficiency of the switching amplifier. The linear amplifier is actuated by an independent voltage source amplifying the envelope input signal, and the switching amplifier is actuated by a dependent current source feeding most of an electric current required for the output of the switching amplifier. An output voltage is controlled by an input voltage, and an output current is a sum of the current of the linear amplifier and the current of the switching amplifier.
Abstract translation: 目的：提供一种使用双开关放大器的效率改进的包络放大器及其设计方法，以减少功耗，从而提高与现有的包络放大器相比的效率。 构成：效率改进的包络放大器包括线性放大器（1）和开关放大器（2）。 开关放大器包括至少两个切换级（21,22），其被包络输入信号的大小选择性地启动。 开关级包括p沟道金属氧化物半导体（PMOS）和n沟道金属氧化物半导体（NMOS）。 包络放大器具有其中线性放大器的线性度和开关放大器的高效率的结构。 线性放大器由放大包络输入信号的独立电压源驱动，并且开关放大器由依赖电流源驱动，馈送开关放大器的输出所需的大部分电流。 输出电压由输入电压控制，输出电流是线性放大器的电流与开关放大器的电流之和。
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公开(公告)号：KR100913424B1
公开(公告)日：2009-08-21
申请号：KR1020080063307
申请日：2008-07-01
Applicant: 한국과학기술원
CPC classification number: G11C11/22
Abstract: A passive matrix-addressable memory apparatus is provided to continually maintain the data state of memory cell by minimizing the interference. A memory device comprises the first electrode line(210), the second electrode line(220), a memory unit(100), and switches(310,320,330). The first electrode line is arranged to be parallel each other. The second electrode lines are arranged to intersect the first electrode lines. The memory unit is arranged between first electrode lines and the second electrode lines. The memory unit has the material which electrically can polarize while having the hysteresis. The switch is arranged between the first electrode lines and the memory unit. The switch is electrically connected to the first electrodes and the memory unit. The first electrodes are electrically connected to the first electrode lines while having the cantilever form. The switch has the second electrodes facing the first electrodes.
Abstract translation: 提供无源矩阵寻址存储装置，通过最小化干扰来连续地维持存储单元的数据状态。 存储器件包括第一电极线（210），第二电极线（220），存储器单元（100）和开关（310,320,330）。 第一电极线被布置为彼此平行。 第二电极线布置成与第一电极线相交。 存储单元布置在第一电极线和第二电极线之间。 存储单元具有能够具有滞后性的电极化的材料。 开关布置在第一电极线和存储器单元之间。 开关电连接到第一电极和存储单元。 第一电极与第一电极线电连接，同时具有悬臂形式。 开关具有面向第一电极的第二电极。
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