公开(公告)号：KR100407193B1

公开(公告)日：2003-11-28

申请号：KR1019990017281

申请日：1999-05-14

Applicant: 한국과학기술원 ,  신성전자공업 주식회사

Inventor： 신형철 ,  유회준 ,  제민규 ,  한승호

IPC: H03B5/30

CPC classification number: H01L27/0629 ,  H03J2200/10 ,  H03L1/026

Abstract: A temperature-adaptive capacitor array used in a TCXO so that the TCXO effectively conducts temperature-compensating in the resonant frequency without the non-monotonicity while a smaller silicon area is used in producing the capacitor array. A number of capacitor arrays allocated in two capacitor banks. Each of the capacitor arrays comprises two or more unit cells, and in turn each unit cell consists of a unit capacitor and a switching element, respectively. All of unit capacitors included in the capacitor arrays are connected each other through a decoder assembly to provide a crystal oscillator with a load capacitance. The unit capacitors belonging to one of the capacitor arrays have the same capacitance with each other. Two unit capacitors belonging to different capacitor arrays, however, have different capacitances from each other. The capacitance of the unit capacitors belonging to each capacitor array is set in consideration of control preciseness required in compensating a frequency deviation in the resonant frequency of the crystal oscillator as the temperature varies in at least a portion of a practical temperature range, within which the crystal oscillator operates.

Abstract translation: 在TCXO中使用的温度自适应电容器阵列使得TCXO有效地在谐振频率下进行温度补偿而没有非单调性，而在生产电容器阵列中使用更小的硅面积。 多个电容器阵列分配在两个电容器组中。 每个电容器阵列包括两个或更多个单元电池，并且每个单元电池又分别由单元电容器和开关元件组成。 包含在电容器阵列中的所有单元电容器通过解码器组件相互连接以提供具有负载电容的晶体振荡器。 属于其中一个电容器阵列的单位电容器具有彼此相同的电容。 然而，属于不同电容器阵列的两个单元电容器具有彼此不同的电容。 考虑到当温度在实际温度范围的至少一部分中变化时补偿晶体振荡器的谐振频率中的频率偏差所需的控制精度，设置属于每个电容器阵列的单位电容器的电容， 晶体振荡器工作。

公开(公告)号：KR1020030020644A

公开(公告)日：2003-03-10

申请号：KR1020010054055

申请日：2001-09-04

Applicant: 한국과학기술원

Inventor： 이종호 ,  신형철

IPC: H01L21/8247 ,  B82Y10/00

CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/785 ,  H01L29/7854 ,  H01L29/7881 ,  H01L29/792

Abstract: PURPOSE: A flash memory device and a method for fabricating the same are provided to improve a scaling-down characteristic, a programming characteristic, and a sustain characteristic by using a structure of a double gate flash memory. CONSTITUTION: An SOI type wafer is formed with a silicon substrate(10), the first oxide layer(22), and a silicon film. The second oxide layer(30) is formed on the silicon film of the SOI type wafer. A Fin active region(26) is formed by forming and etching the second oxide layer pattern. A gate tunneling oxide layer(42) is formed on both sides and an upper portion of the Fin active region(26). A floating electrode(32) is formed on the gate tunneling oxide layer(42) and surfaces of the first and the second oxide layers(22,30). An intergate oxide(34) is formed on a surface of the floating electrode(32). A control electrode(36) is formed on a surface of the intergate oxide(34).

Abstract translation: 目的：提供一种闪存器件及其制造方法，以通过使用双栅极闪存的结构来提高缩小特性，编程特性和维持特性。 构成：SOI型晶片形成有硅衬底（10），第一氧化物层（22）和硅膜。 第二氧化物层（30）形成在SOI型晶片的硅膜上。 通过形成和蚀刻第二氧化物层图案形成翅片活动区域（26）。 栅极隧道氧化物层（42）形成在鳍片活动区域（26）的两侧和上部。 在栅极隧穿氧化物层（42）和第一和第二氧化物层（22,30）的表面上形成浮动电极（32）。 在浮动电极（32）的表面上形成有栅极间氧化物（34）。 在栅间氧化物（34）的表面上形成控制电极（36）。

公开(公告)号：KR100319449B1

公开(公告)日：2002-01-05

申请号：KR1019990012742

申请日：1999-04-12

Applicant: 한국과학기술원

Inventor： 신형철 ,  이종호 ,  한상연

IPC: H01L21/334

Abstract: 본발명은극소채널소자의제조방법에관한것이며, 특히주 게이트와일함수에있어서차이가나는측면게이트를사용함으로써측면게이트아래에형성되는채널이얇은소스/드레인영역의역할을할 수있도록하며, 채널영역의도우핑을줄여캐리어의이동도를개선하고문턱전압조정을위해주입된불순물의비균일성으로인한문턱전압의변화를최소화할수 있도록하는극소채널소자의제조방법를제공하는데그 목적이있다. 또한, 본발명에따르면, 극소채널소자의제조방법에있어서, p-기판위에게이트산화막을형성한후 극소패터닝기술을이용하여 p+ 다결정실리콘주 게이트를정의하는단계; 상기결과물위에절연막을입힌후에, 주게이트와절연막을개재하여 n+ 다결정실리콘측면게이트를정의하는단계; 및상기측면게이트의양 측면에 p할로이온을주입한후에, 소스/드레인 n+ 이온을주입하는단계를포함하여이루어진극소채널소자의제조방법이제공된다.