公开(公告)号：KR100457177B1

公开(公告)日：2004-11-16

申请号：KR1020030013788

申请日：2003-03-05

Applicant: 한국전자통신연구원

Inventor： 홍도원 ,  류희수 ,  신상욱 ,  장구영 ,  정석원 ,  윤중철 ,  최준 ,  임종인

IPC: G06F7/52

Abstract: PURPOSE: A serial-parallel multiplier finding out the multiplication of two elements on a finite field is provided to quickly find out the multiplication of two elements on finite field by performing the modular subtraction for each operation result again after respectively multiplying the divided two multipliers to a multiplicand. CONSTITUTION: A multiplexer(11) alternatively outputs the first and the second multiplier data depending on a selection signal by receiving the multiplier data in parallel. A half multiplier(12) outputs the first operation value by multiplying the first multiplier to the multiplicand data and performing the modular operation, and outputs the second operation value by multiplying the second multiplier to the multiplicand data and performing the modular operation. A storage(13) stores the first operation value at the first cycle and outputs the stored value at the second cycle depending on a clock doubled to the selection signal. A modular subtracter(14) performs the modular subtraction for subtracting the received first operation value from the second operation value.

Abstract translation: 目的：通过在分开的两个乘法器分别乘以各个运算结果之后再次对每个运算结果进行模减法，提供一个求出有限域上两个元素相乘的串行 - 并行乘法器，以快速找出两个元素在有限域上的乘法 被乘数。 构成：复用器（11）通过并行接收乘法器数据，根据选择信号交替地输出第一和第二乘法器数据。 半乘法器（12）通过将第一乘数与乘数数据相乘并执行模运算来输出第一运算值，并且通过将第二乘数与乘数数据相乘并执行模运算来输出第二运算值。 存储器（13）在第一周期存储第一操作值，并根据加倍到选择信号的时钟在第二周期输出存储的值。 模块减法器（14）执行模减法以从第二操作值中减去接收到的第一操作值。

公开(公告)号：KR1020040053833A

公开(公告)日：2004-06-25

申请号：KR1020020080285

申请日：2002-12-16

Applicant: 한국전자통신연구원

Inventor： 최용제 ,  김호원 ,  김무섭 ,  류희수

IPC: H04L9/00

CPC classification number: H04L9/3066

Abstract: PURPOSE: A high-performance encryption device using an elliptic curve is provided to process rapidly a scalar multiplication calculation process by optimizing an elliptic curve calculation method and a window calculation method on a projective coordinate system. CONSTITUTION: A first storage(100) stores multiplication constant k and outputs it at scalar multiplication calculation using a comb method and a multiplication constant of scalar multiplication calculation using a window method. A second storage(300,400) stores input coordinates of an elliptic curve, a result of intermediate calculation, and a result of final calculation. A third storage(500) converts affine coordinates to projective coordinates and the result of intermediate calculation. A fourth storage(600,700) stores new coordinates to perform an addition calculation process of the elliptic curve. A multiplication calculation unit(2000,2100,2200,2300) performs a multiplication calculation process of finite field. A reciprocal calculation unit(2400) performs a reciprocal calculation process of the finite field. An additional calculation unit(1300) calculates various elliptic curves by using the multiplication calculation and the reciprocal calculation unit. A multiplexer unit(800-1000,1500-1900) selects an input of the storage and the inputs of the multiplication calculation and the reciprocal calculation unit. A control unit(1100) performs all operations of each element.

Abstract translation: 目的：提供一种使用椭圆曲线的高性能加密装置，通过在投影坐标系上优化椭圆曲线计算方法和窗口计算方法，快速处理标量乘法运算过程。 构成：第一存储器（100）存储倍数常数k，并使用梳状方法和使用窗口方法的标量乘法运算的乘法常数在标量乘法运算中输出。 第二存储器（300,400）存储椭圆曲线的输入坐标，中间计算的结果和最终计算的结果。 第三个存储（500）将仿射坐标转换为投影坐标，并将中间计算结果转换为投影坐标。 第四存储器（600,700）存储新坐标以执行椭圆曲线的加法运算处理。 乘法运算单元（2000,2100,2200,2300）进行有限域的乘法运算处理。 倒数计算单元（2400）执行有限域的倒数计算处理。 附加计算单元（1300）通过使用乘法运算和倒数计算单元计算各种椭圆曲线。 复用器单元（800-1000,1500-1900）选择存储器的输入和乘法运算的输入以及倒数计算单元。 控制单元（1100）执行每个元件的所有操作。

公开(公告)号：KR1020040052304A

公开(公告)日：2004-06-23

申请号：KR1020020080156

申请日：2002-12-16

Applicant: 한국전자통신연구원

Inventor： 김호원 ,  김무섭 ,  최용제 ,  류희수 ,  정교일

IPC: G06F1/00

Abstract: PURPOSE: A device and a method for the security of a digital hardware system are provided to encrypt/decrypt data fast by using an exclusive binary operator and a similar random number generator, offer the high security by using an asymmetric encryption algorithm, and reinforce the security of the digital hardware system such as a set-top box or a digital game machine. CONSTITUTION: A hardware block(110) having a hardware security mechanism is equipped with a security target block(100) that is the security target of a CPU or a PCI(Peripheral Component Interconnect) bridge, and a hardware security block(120) providing the hardware security mechanism and performing bidirectional communication while providing the stability for data and an instruction through a hardware system bus(130). The hardware security block includes a key distribution controller(140), a controller(150), the similar random number generator(160), the exclusive binary operator(170), and the asymmetric encryption module(180).

Abstract translation: 目的：提供一种用于数字硬件系统安全的设备和方法，通过使用独有的二进制运算符和类似的随机数生成器快速加密/解密数据，通过使用非对称加密算法提供高安全性，并加强 诸如机顶盒或数字游戏机的数字硬件系统的安全性。 构成：具有硬件安全机制的硬件块（110）配备有作为CPU或PCI（外围组件互连）桥的安全目标的安全目标块（100）和提供 硬件安全机制并执行双向通信，同时通过硬件系统总线提供数据的稳定性和指令（130）。 硬件安全块包括密钥分配控制器（140），控制器（150），类似的随机数生成器（160），专用二进制运算符（170）和非对称加密模块（180）。

公开(公告)号：KR1020040037555A

公开(公告)日：2004-05-07

申请号：KR1020020066100

申请日：2002-10-29

Applicant: 한국전자통신연구원

Inventor： 김무섭 ,  최용제 ,  김호원 ,  류희수 ,  정교일

IPC: G06Q20/38 ,  G06F7/552

CPC classification number: G06F7/50 ,  G06F7/722 ,  H04L9/302

Abstract: PURPOSE: A device and a method for operating modular, and an RAS(Rivest-Shamir-Adleman) operating system for the same are provided to improve efficiency of a modular operation for the RSA encryption operation of the system having a low-operation frequency. CONSTITUTION: The RSA operator(110) comprises data selection parts(200, 210), a modular operator(220), and a path selection part(230). The data selection parts(200, 210) select a data between a data from an input interface(100), and a data received from the path selection part(230). The modular operator(220) comprises a modular multiplier(220-1) and a reduction part(220-2). The modular multiplier(220-1) performs a Montgomery operation. The reduction part(220-2) performs third step of a formula 3. The path selection part(230) provides result value of each modular operations to the data selection parts(200, 210) while the modular operation is executed. The path selection part(230) outputs result value when the modular operation is terminated.

Abstract translation: 目的：提供一种用于操作模块化的设备和方法，以及用于其的RAS（Rivest-Shamir-Adleman）操作系统，以提高具有低操作频率的系统的RSA加密操作的模块化操作的效率。 构成：RSA操作器（110）包括数据选择部件（200,210），模块化操作器（220）和路径选择部件（230）。 数据选择部分（200,210）选择来自输入接口（100）的数据和从路径选择部分（230）接收的数据之间的数据。 模块化操作器（220）包括模数乘法器（220-1）和减速部分（220-2）。 模块化乘法器（220-1）执行蒙哥马利运算。 还原部分（220-2）执行公式3的第三步骤。当执行模块化操作时，路径选择部分（230）向数据选择部分（200,210）提供每个模块化操作的结果值。 当模块化操作终止时，路径选择部分（230）输出结果值。

公开(公告)号：KR1020040033158A

公开(公告)日：2004-04-21

申请号：KR1020020062076

申请日：2002-10-11

Applicant: 한국전자통신연구원

Inventor： 신상욱 ,  류희수 ,  홍도원 ,  정배은 ,  강주성 ,  장구영 ,  김건우 ,  김재겸 ,  손호준

IPC: H04L9/00

CPC classification number: H04L9/0662 ,  G06F7/582 ,  H04L9/001 ,  H04W12/08

Abstract: PURPOSE: An encrypting and decrypting method using cellular automata and an apparatus for the same are provided to encrypt and decrypt input data by using structural merits of multi-dimensional cellular automata. CONSTITUTION: A multi-dimensional space is formed by using a plurality of triangular cells(201). Binary digits having predetermined bits are assigned to the triangular cells, respectively(202). Each value of the triangular cells is updated according to the flow of discrete time and a binary random progression is formed by using each value of the triangular cells(207). An encryption process is performed by executing a logical operation for the binary random progression and a plain text binary progression(208).

Abstract translation: 目的：提供使用细胞自动机的加密和解密方法及其装置，通过使用多维细胞自动机的结构优点对输入数据进行加密和解密。 构成：通过使用多个三角形单元（201）形成多维空间。 具有预定位的二进制数字分别被分配给三角形单元（202）。 根据离散时间的流程更新三角形单元的每个值，并且通过使用三角形单元格的每个值（207）形成二进制随机进度。 通过执行二进制随机进程和纯文本二进制进程的逻辑运算来执行加密处理（208）。

公开(公告)号：KR1020020051597A

公开(公告)日：2002-06-29

申请号：KR1020000080993

申请日：2000-12-23

Applicant: 한국전자통신연구원

Inventor： 신상욱 ,  이옥연 ,  류희수 ,  이경현

IPC: H04L9/18

CPC classification number: H04L9/302

Abstract: PURPOSE: A data encryption system using an asymmetric encryption algorithm and a method thereof are provided, which provides a data secret and a data robustness by encrypting a large quantity of messages in a high speed without additional shared encryption key exchange step. CONSTITUTION: According to the data encryption system, an AONT(All-Or-Nothing) conversion part(105) converts input data into a pseudo message using an All-or-nothing method based on a hash function(103). An OAE(Optimal Asymmetric Encryption) part(111) encrypts a part of the pseudo message converted by the above AONT conversion part using the hash function and an asymmetric encryption algorithm. The above AONT conversion part includes a unit calculating an intermediate byproduct K using a divided input message X and N of n-bit nonce(Random Number) after dividing the input message X, and a unit calculating the pseudo message from the above K.

Abstract translation: 目的：提供一种使用非对称加密算法及其方法的数据加密系统，其通过在没有额外的共享加密密钥交换步骤的情况下高速加密大量消息来提供数据秘密和数据鲁棒性。 构成：根据数据加密系统，AONT（All-Or-Nothing）转换部分（105）使用基于散列函数（103）的全无变换方法将输入数据转换为伪消息。 OAE（最优非对称加密）部分（111）使用散列函数和非对称加密算法加密由上述AONT转换部分转换的伪消息的一部分。 上述AONT转换部分包括在划分输入消息X之后使用分割输入消息X和n位随机数（随机数）N计算中间副产品K的单元，以及从上述K计算伪消息的单元。