-
Patent Agency Ranking
公开(公告)号：KR1019960024902A
公开(公告)日：1996-07-20
申请号：KR1019940034005
申请日：1994-12-13
Applicant: 한국전자통신연구원
IPC: G06F7/44
Abstract: 본 발명은 단차 승산수단(107)과, 승산수단(110)과, 가산수단(112)과, 드라이버(101)를 구비하는 것을 특징으로 하는 유한체(Finite field) 갈로아체(GF(2
n )) 승산기 및 그 승산방법에 관한 것으로, 특히 현재 세계적으로 각광을 받고 있으나, 그의 실현이 난이한 공개키 암호 시스템을 쉽게 구현할 수 있는 효과를 얻을 수 있다.-
公开(公告)号：KR1020080051773A
公开(公告)日：2008-06-11
申请号：KR1020060123392
申请日：2006-12-06
Applicant: 한국전자통신연구원
CPC classification number: G06F7/725 , G06F2207/7261
Abstract: A scalar multiplication method for simultaneously performing recoding and scalar multiplication with left-to-right direction safe to SPA is provided to securely perform an SPA(Simple Power Analysis) without separately storing a result recoded after combining a recoding process and a scalar multiplication to a private key. A scalar multiplication method for simultaneously performing recoding and scalar multiplication with left-to-right direction safe to SPA includes a step of recoding by comparing two continued elements which overlap is permitted from most significant digit of an n-digit private key represented with r system such that an L-digit private key is created(S120,S130,S140). A scalar multiplication result value is calculated with scalar-multiplying the private key to a predetermined point on a curve of an ellipse by using the recoded private key(S190). The private key is initialized by comparing the n-digit private key and the L-digit private key. The L-digit private key is created by comparing two continued elements which overlap is permitted from most significant digit of an initialized private key.
Abstract translation: 提供了一种用于同时执行从左到右方向安全到SPA的重新编码和标量乘法的标量乘法，以安全地执行SPA（简单功率分析），而不需要在将重新编码过程和标量乘法组合之后重新编码的结果存储到 私钥。 用于同时执行从左到右方向对SPA安全的重新编码和标量乘法的标量乘法包括通过比较由r系统表示的n位专用密钥的最高有效位允许的两个连续元素进行重新编码的步骤 使得创建L数字私钥（S120，S130，S140）。 通过使用重新编码的私钥（S190），通过将私钥标量乘以椭圆曲线上的预定点来计算标量乘法结果值。 通过比较n位私钥和L位私钥来初始化私钥。 通过比较两个继续元素创建L位私钥，这些元素可以从初始化私钥的最高有效位允许重叠。
-
公开(公告)号：KR1020040055550A
公开(公告)日：2004-06-26
申请号：KR1020030013788
申请日：2003-03-05
Applicant: 한국전자통신연구원
IPC: G06F7/52
Abstract: PURPOSE: A serial-parallel multiplier finding out the multiplication of two elements on a finite field is provided to quickly find out the multiplication of two elements on finite field by performing the modular subtraction for each operation result again after respectively multiplying the divided two multipliers to a multiplicand. CONSTITUTION: A multiplexer(11) alternatively outputs the first and the second multiplier data depending on a selection signal by receiving the multiplier data in parallel. A half multiplier(12) outputs the first operation value by multiplying the first multiplier to the multiplicand data and performing the modular operation, and outputs the second operation value by multiplying the second multiplier to the multiplicand data and performing the modular operation. A storage(13) stores the first operation value at the first cycle and outputs the stored value at the second cycle depending on a clock doubled to the selection signal. A modular subtracter(14) performs the modular subtraction for subtracting the received first operation value from the second operation value.
Abstract translation: 目的：提供一个串行和并行乘法器，找出有限域上的两个元素的乘法，以便通过在将分割的两个乘法器分别乘以后，再次对每个运算结果执行模式减法，快速找出有限域上的两个元素的乘法 被乘数 构成：多路复用器（11）通过并行地接收乘法器数据来交替地输出取决于选择信号的第一和第二乘法器数据。 半乘法器（12）通过将第一乘法器与被乘数数据相乘并执行模数运算来输出第一运算值，并且通过将第二乘法器乘以乘法数据并执行模数运算来输出第二运算值。 存储器（13）在第一周期存储第一操作值，并且根据与选择信号相加的时钟在第二周期输出存储的值。 模块减法器（14）执行模式减法，以从第二操作值减去接收到的第一操作值。
-
公开(公告)号：KR100867989B1
公开(公告)日：2008-11-10
申请号：KR1020060123392
申请日：2006-12-06
Applicant: 한국전자통신연구원
CPC classification number: G06F7/725 , G06F2207/7261
Abstract: 본 발명은 단순전력분석에 안전한 Left-to-Right 리코딩 기법과 통합된 스칼라 곱셈 방법에 관한 것으로, 타원곡선 암호시스템과 페어링을 기반하는 암호시스템에서 사용되는 스칼라 곱셈 방법에 있어서, r진법으로 표현된 n-digit 비밀키(k)의 최상위 digit부터 중복을 허용한 2개의 연속된 원소를 비교하여 L-digit 비밀키(k')가 생성되도록 리코딩하는 단계 및 상기 리코딩된 비밀키(k')를 이용하여 상기 비밀키(k)와 상기 타원곡선 상의 임의의 점 P에 스칼라 곱셈하여 스칼라 곱셈 결과값(Q)을 산출하는 단계로 구성되어, 스칼라 곱셈 알고리즘을 부채널 공격, 특히 단순전력분석 공격에 안전하도록 기수 r진법으로 표현된 비밀키의 표현을 부호화를 이용해 리코딩 단계와 스칼라 곱셈 단계를 동시에 수행할 수 있게 하여 메모리의 제약을 받는 유비쿼터스 컴퓨팅 환경에서 부채널 공격에 안전하면서 메모리의 사용을 최대한 줄일 수 있는 기술적인 해결 방법을 제시한다.
타원곡선, 페어링, 암호시스템, 부채널 공격, Left-to-Right 리코딩-
公开(公告)号：KR100457177B1
公开(公告)日：2004-11-16
申请号：KR1020030013788
申请日：2003-03-05
Applicant: 한국전자통신연구원
IPC: G06F7/52
Abstract: PURPOSE: A serial-parallel multiplier finding out the multiplication of two elements on a finite field is provided to quickly find out the multiplication of two elements on finite field by performing the modular subtraction for each operation result again after respectively multiplying the divided two multipliers to a multiplicand. CONSTITUTION: A multiplexer(11) alternatively outputs the first and the second multiplier data depending on a selection signal by receiving the multiplier data in parallel. A half multiplier(12) outputs the first operation value by multiplying the first multiplier to the multiplicand data and performing the modular operation, and outputs the second operation value by multiplying the second multiplier to the multiplicand data and performing the modular operation. A storage(13) stores the first operation value at the first cycle and outputs the stored value at the second cycle depending on a clock doubled to the selection signal. A modular subtracter(14) performs the modular subtraction for subtracting the received first operation value from the second operation value.
Abstract translation: 目的：通过在分开的两个乘法器分别乘以各个运算结果之后再次对每个运算结果进行模减法，提供一个求出有限域上两个元素相乘的串行 - 并行乘法器，以快速找出两个元素在有限域上的乘法 被乘数。 构成：复用器（11）通过并行接收乘法器数据，根据选择信号交替地输出第一和第二乘法器数据。 半乘法器（12）通过将第一乘数与乘数数据相乘并执行模运算来输出第一运算值，并且通过将第二乘数与乘数数据相乘并执行模运算来输出第二运算值。 存储器（13）在第一周期存储第一操作值，并根据加倍到选择信号的时钟在第二周期输出存储的值。 模块减法器（14）执行模减法以从第二操作值中减去接收到的第一操作值。
-
-
-
-
Search Results
5
records
(took 0.016 seconds)
