公开(公告)号：KR100457177B1

公开(公告)日：2004-11-16

申请号：KR1020030013788

申请日：2003-03-05

Applicant: 한국전자통신연구원

Inventor： 홍도원 ,  류희수 ,  신상욱 ,  장구영 ,  정석원 ,  윤중철 ,  최준 ,  임종인

IPC: G06F7/52

Abstract: PURPOSE: A serial-parallel multiplier finding out the multiplication of two elements on a finite field is provided to quickly find out the multiplication of two elements on finite field by performing the modular subtraction for each operation result again after respectively multiplying the divided two multipliers to a multiplicand. CONSTITUTION: A multiplexer(11) alternatively outputs the first and the second multiplier data depending on a selection signal by receiving the multiplier data in parallel. A half multiplier(12) outputs the first operation value by multiplying the first multiplier to the multiplicand data and performing the modular operation, and outputs the second operation value by multiplying the second multiplier to the multiplicand data and performing the modular operation. A storage(13) stores the first operation value at the first cycle and outputs the stored value at the second cycle depending on a clock doubled to the selection signal. A modular subtracter(14) performs the modular subtraction for subtracting the received first operation value from the second operation value.

Abstract translation: 目的：通过在分开的两个乘法器分别乘以各个运算结果之后再次对每个运算结果进行模减法，提供一个求出有限域上两个元素相乘的串行 - 并行乘法器，以快速找出两个元素在有限域上的乘法 被乘数。 构成：复用器（11）通过并行接收乘法器数据，根据选择信号交替地输出第一和第二乘法器数据。 半乘法器（12）通过将第一乘数与乘数数据相乘并执行模运算来输出第一运算值，并且通过将第二乘数与乘数数据相乘并执行模运算来输出第二运算值。 存储器（13）在第一周期存储第一操作值，并根据加倍到选择信号的时钟在第二周期输出存储的值。 模块减法器（14）执行模减法以从第二操作值中减去接收到的第一操作值。

公开(公告)号：KR1020040055550A

公开(公告)日：2004-06-26

申请号：KR1020030013788

申请日：2003-03-05

Applicant: 한국전자통신연구원

Inventor： 홍도원 ,  류희수 ,  신상욱 ,  장구영 ,  정석원 ,  윤중철 ,  최준 ,  임종인

IPC: G06F7/52

Abstract: PURPOSE: A serial-parallel multiplier finding out the multiplication of two elements on a finite field is provided to quickly find out the multiplication of two elements on finite field by performing the modular subtraction for each operation result again after respectively multiplying the divided two multipliers to a multiplicand. CONSTITUTION: A multiplexer(11) alternatively outputs the first and the second multiplier data depending on a selection signal by receiving the multiplier data in parallel. A half multiplier(12) outputs the first operation value by multiplying the first multiplier to the multiplicand data and performing the modular operation, and outputs the second operation value by multiplying the second multiplier to the multiplicand data and performing the modular operation. A storage(13) stores the first operation value at the first cycle and outputs the stored value at the second cycle depending on a clock doubled to the selection signal. A modular subtracter(14) performs the modular subtraction for subtracting the received first operation value from the second operation value.

Abstract translation: 目的：提供一个串行和并行乘法器，找出有限域上的两个元素的乘法，以便通过在将分割的两个乘法器分别乘以后，再次对每个运算结果执行模式减法，快速找出有限域上的两个元素的乘法 被乘数 构成：多路复用器（11）通过并行地接收乘法器数据来交替地输出取决于选择信号的第一和第二乘法器数据。 半乘法器（12）通过将第一乘法器与被乘数数据相乘并执行模数运算来输出第一运算值，并且通过将第二乘法器乘以乘法数据并执行模数运算来输出第二运算值。 存储器（13）在第一周期存储第一操作值，并且根据与选择信号相加的时钟在第二周期输出存储的值。 模块减法器（14）执行模式减法，以从第二操作值减去接收到的第一操作值。