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公开(公告)号：KR1019920003285B1
公开(公告)日：1992-04-27
申请号：KR1019890019305
申请日：1989-12-22
Applicant: 한국전자통신연구원
IPC: G06F13/00
Abstract: transmissions of ordinary reading and writing, reading for reading, reading for writing, write-back and invalid cash identity and transmissions of interlock reading, and interlock writing for processor-read data corrections. The transmissions are carried out through a requestor (10) and a responder (20). The method transmits data by breaking down into above mentioned forms, so that the translating section of the receiving end recognizes the cause of the data source and its purpose.
Abstract translation: 普通阅读和写作的读取，阅读阅读，写作阅读，回写和无效现金身份以及联锁读取的传输，以及用于处理器读取数据更正的联锁写入。 传输通过请求者（10）和响应者（20）进行。 该方法通过分解成上述形式发送数据，使得接收端的翻译部分识别数据源的原因及其目的。
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公开(公告)号：KR1019920000479B1
公开(公告)日：1992-01-14
申请号：KR1019890019311
申请日：1989-12-22
Applicant: 한국전자통신연구원
IPC: G06F13/00
Abstract: The read modify write (RMW) is executed not occupying system bus for synchronizing the processors of multi process system. The method includes the steps: (A) checking RMW transmission type in a data transmission type generator and a data transmission bus requester (3); (B) discriminating the write or read operation of RMW; (C) executing interlock read operation and receiving AACK signal at RMW read operation; otherwise (D) executing interlock write operation, and checking the locking state using a locking transmission type processor and data transmission bus interfacer (5); (E) sending lock busy signal and OK signal to the bus requester when the bus is locked by the interlock read; and (F) when the bus is locked by the interlock write, sending OK signal, releasing the lock, writing data and sending error signal at the same time.
Abstract translation: 执行读修改写（RMW）不占用用于同步多进程系统的处理器的系统总线。 该方法包括以下步骤：（A）检查数据传输类型发生器和数据传输总线请求器（3）中的RMW传输类型; （B）识别RMW的写入或读取操作; （C）执行联锁读操作，并以RMW读操作接收AACK信号; 否则（D）执行联锁写入操作，并使用锁定传输类型处理器和数据传输总线接口（5）检查锁定状态; （E）当总线被互锁读取锁定时，向总线请求者发送锁定忙信号和OK信号; 和（F）当总线通过互锁写入锁定时，发送OK信号，释放锁定，同时写入数据和发送错误信号。
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Patent Agency Ranking
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公开(公告)号：KR1019940009755B1
公开(公告)日：1994-10-17
申请号：KR1019910024250
申请日：1991-12-24
Applicant: 한국전자통신연구원
IPC: G06F9/00
Abstract: The memory board contains an initialization control circuit (30) to remove an error due to random check bits during the access of data in the memory after supply of power. The circuit writes an initial value into data storage area and error correction area of a memory (10) as soon as power is supplied. The memory board also contains an error correction and detection module (20), a binary counter (40) to generate the memory address during the initialization, and a register (60) to store "0" value into data area of memory during the initialization.
Abstract translation: 存储器板包含初始化控制电路（30），用于在供电之后在存储器中的数据访问期间消除由于随机校验位导致的错误。 一旦电力供应，电路将初始值写入存储器（10）的数据存储区域和纠错区域。 存储器板还包含纠错和检测模块（20），用于在初始化期间产生存储器地址的二进制计数器（40）以及在初始化期间将“0”值存储到存储器的数据区域中的寄存器（60） 。
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