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公开(公告)号：KR1019940003331B1
公开(公告)日：1994-04-20
申请号：KR1019910023520
申请日：1991-12-19
Applicant: 한국전자통신연구원
IPC: G06F13/16
Abstract: The method points the bottleneck part in the multiprocessor system, detects the floating point arithmetic and input-output synchronization, and verifies the scheduling equity of operating system and appropriate distribution. The method a employing a system controller (1), a main memory device (2), a processor group (3) and a system bus (4), includes the steps of: load processor generation; completion signal generation; saving and outputting state information; symmetricity determination; and saving and outputting results.
Abstract translation: 该方法指出了多处理器系统中的瓶颈部分，检测浮点算术和输入输出同步，验证了操作系统的调度权益和适当的分配。 采用系统控制器（1），主存储器（2），处理器组（3）和系统总线（4）的方法包括以下步骤：加载处理器生成; 完成信号发生; 保存和输出状态信息; 对称性确定 并保存并输出结果。
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公开(公告)号：KR1019920001815B1
公开(公告)日：1992-03-03
申请号：KR1019890019309
申请日：1989-12-22
Applicant: 한국전자통신연구원
IPC: G06F13/24
Abstract: checking whether there is an interrupt transmission request from one of processors (1) and (2) to an interrupt requestor (4); checking whether an interrupt bus synchronizing signal is true; waiting until the interrupt bus synchronizing signal becomes false by being fed-back if the signal is true; issuing a use request for the interrupt bus (3) if the signal is false; transmitting an interrupt to the interrupt bus (3) by utilizing one of interrupt processors (5) and (6); checking whether the transmission of the interrupt has been completed; and terminating the interrupt transmission by inputting an interrupt synchronizing signal through a signal line (6b).
Abstract translation: 检查处理器（1）和（2）之一是否存在到中断请求者（4）的中断传输请求; 检查中断总线同步信号是否为真; 如果信号为真，则等待中断总线同步信号通过反馈变为假; 如果信号为假，则发出中断总线（3）的使用请求; 通过利用中断处理器（5）和（6）之一向中断总线（3）发送中断; 检查中断的传输是否已经完成; 并通过信号线（6b）输入中断同步信号来终止中断发送。
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Patent Agency Ranking
公开(公告)号：KR100174865B1
公开(公告)日：1999-04-01
申请号：KR1019900021875
申请日：1990-12-26
Applicant: 한국전자통신연구원
Abstract: 본 발명은 행정전산망의 주전산기에 있어서, 계정을 관리하는 시스템의 계정관리 방법에 관한 것으로서, 상태 검사 버튼, 계정등록용 항목 및 수행 버튼의 클릭여부에 따라 해당항목의 상태값 표시, 계정등록의 입력 및 계정 이름과 번호의 입력을 각각 수행하도록 하여 소정화일에 계정을 등록하는 계정등록과정; 상기 계정등록스텝과 동일한 처리 수순에 따라 소정화일에 계정을 삭제토록하는 계정삭제과정; 상기 계정등록스텝과 동일한 처리 수순에 따라 디스플레이 되게 한 다음 계정변경용 항목 및 수행 버튼의 클릭여부에 따라 계정변경항목의 입력과 소정화일에 계정변경을 각각 수행토록 하는 계정변경과정과; 초기화면의 처리를 거친 다음 수행 버튼의 클릭여부에 따라 소정화일에서 계정등록상황을 디스플레이 되게 하는 계정열람과정을 포함하여 된 것을 특징으로 한다.
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公开(公告)号：KR1019940005025B1
公开(公告)日：1994-06-09
申请号：KR1019900017339
申请日：1990-10-29
Applicant: 한국전자통신연구원
IPC: H04L12/933 , H04L12/947
Abstract: The switching device comprises a queue logic for temporarily storing input data; a path select logic for selecting a path to transmit the data transmitted through the queue logic to the next stage; and a control logic for controlling the queue logic and the path select logic, thereby simplifying a communication path.
Abstract translation: 切换装置包括用于临时存储输入数据的队列逻辑; 路径选择逻辑，用于选择将通过队列逻辑传输的数据传送到下一级的路径; 以及用于控制队列逻辑和路径选择逻辑的控制逻辑，从而简化通信路径。
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公开(公告)号：KR1019930007049B1
公开(公告)日：1993-07-26
申请号：KR1019900021814
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F15/16
Abstract: The arbitrator processes independent data transmission processes of several handlers without mutual interruption to improve the efficiency of bus. It includes a control logic of address bus arbitration (1) for controlling arbitration, a multiplexer (2) for applying request signal (req) to one of the signal lines (ABRQ0-ABRQ12), a priority encoder (4) for detecting the signal of the highest priority, a 4 bit comparator (5) for comparing the output of the priority encoder (4) with its slot address signal (3), and an equity flag (6) for being checked to maintain the equity of address bus usage.
Abstract translation: 仲裁员处理多个处理程序的独立数据传输过程，而不会相互中断，从而提高总线的效率。 它包括用于控制仲裁的地址总线仲裁（1）的控制逻辑，用于向信号线（ABRQ0-ABRQ12）中的一条应用请求信号（req）的复用器（2），用于检测信号的优先级编码器 优先权编码器（4）的输出与其时隙地址信号（3）进行比较的4比特比较器（5）和被检查以维持地址总线使用权益的权利标志（6） 。
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