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公开(公告)号：KR1019940002274B1
公开(公告)日：1994-03-19
申请号：KR1019900021838
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F11/16
Abstract: The circuit comprises input/output units for processing commands and data, a instantaneous data expansion processing circuit which expands into zero the upper 16 bits of the command register from the register file, allows the lower 16 bit to have the output data of the lower 16 bits of the command register and generates data signals by selecting the B port data of the register file, and a operation circuit which performs logic multiplication of the two data signals from the aforementioned circuit.
Abstract translation: 该电路包括用于处理命令和数据的输入/输出单元，瞬时数据扩展处理电路，从寄存器堆扩展到命令寄存器的高16位，为零，允许低16位具有下16位的输出数据 命令寄存器的位，并且通过选择寄存器堆的B端口数据来生成数据信号，以及执行来自前述电路的两个数据信号的逻辑乘法运算电路。
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公开(公告)号：KR1019930002789B1
公开(公告)日：1993-04-10
申请号：KR1019900021837
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F13/40
Abstract: The circuit expands variable length of data in a 32 bit microprocessor to simplify the variation of word length. It includes a two input multiplexer (1) for selecting half-word data (31...0 or 32...16) according to the address signal (A1) for bite-positioning, a four input multiplexer (2), a multiplexer (3) for selecting code, and an expansion multiplexer (5) for selecting one of the data, which is zero expanded, code expanded or original code.
Abstract translation: 该电路在32位微处理器中扩展了可变长度的数据，以简化字长的变化。 它包括用于根据用于咬定位的地址信号（A1）来选择半字数据（31 ... 0或32 ... 16）的双输入多路复用器（1），四输入多路复用器（2）， 用于选择代码的多路复用器（3）和用于选择零扩展，代码扩展或原始代码的数据之一的扩展多路复用器（5）。
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Patent Agency Ranking
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公开(公告)号：KR1019930007042B1
公开(公告)日：1993-07-26
申请号：KR1019900021827
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F9/34
Abstract: The type valid signal generating circuit generating a signal for designating size and position of byte, halfword and word according to byte address designating signal and big endian/little endian byte selection signals. The circuit comprises an input stage comprising inverters (I1-I4), NOR gates (N1-N4), and 4-input 1- output multiplexers (1-4) for designating byte size according to byte address designating signals (A0,A1) and big endian/little endian bus selection signal (BLB), an exclusive OR and an exclusive NOR gate (EX1,EX2) for designating byte size for halfword request signal input, multiplexers (5-8) for generating size of byte, halfword, and word for memory access request signal, and a multiplexer (S) for outputting data byte request signal (DBE) according to pixel instruction address selection signal (IPST) and output signals of the multiplexers (5-8).
Abstract translation: 类型有效信号发生电路根据字节地址指定信号和大端/小端字节选择信号产生用于指定字节，半字和字的大小和位置的信号。 该电路包括一个输入级，包括根据字节地址指定信号（A0，A1）指定字节大小的反相器（I1-I4），或非门（N1-N4）和4-输入1-输出多路复用器（1-4） 和大端/小端总线选择信号（BLB），用于指定半字请求信号输入的字节大小的异或和异或（或非门）（EX1，EX2），用于生成字节大小的半复用器（5-8） 和用于存储器访问请求信号的字，以及用于根据像素指令地址选择信号（IPST）和多路复用器（5-8）的输出信号输出数据字节请求信号（DBE）的复用器（S）。
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公开(公告)号：KR1019930007015B1
公开(公告)日：1993-07-26
申请号：KR1019900021822
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F9/38
Abstract: The circuit is for inputting and outputting correct data value in a processor using a 3 step pipe line. It includes 3 multiplexers (1,2,3) for receiving internal control input ?(RA-A,RA-B),(RB-A,RB-B),(RC-A,RC-B)?-00,10,01,11-through their A inputs and controlling outputs (A,W,B,C).
Abstract translation: 该电路用于使用3段管线在处理器中输入和输出正确的数据值。 它包括3个用于接收内部控制输入（RA-A，RA-B），（RB-A，RB-B），（RC-A，RC-B） 通过其A输入和控制输出（A，W，B，C）10,101,11。
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