WORDLINE DRIVER FOR FLASH MEMORY READ MODE
    21.
    发明公开
    WORDLINE DRIVER FOR FLASH MEMORY READ MODE 有权
    字线驱动器闪存读取模式下的

    公开(公告)号:EP1258007A1

    公开(公告)日:2002-11-20

    申请号:EP01908956.4

    申请日:2001-02-07

    CPC classification number: G11C16/08 G11C8/08

    Abstract: The present invention discloses a wordline voltage regulation method and system that provides a predetermined voltage as a wordline voltage to a plurality of wordlines (18) during read mode. A supply voltage (Vcc) is regulated and temperature compensated by a wordline driver circuit (16) to provide the predetermined voltage that is lower in magnitude than the magnitude of the supply voltage (Vcc). The wordline driver circuit (16) is activated by an activation circuit (12) when the read operation is initiated. During the read operation, the wordline driver circuit (16) maintains the predetermined voltage during variations in the supply voltage (Vcc) as well as variations in a process load supplied by the wordline driver circuit (16).

    FLASH MEMORY ARCHITECTURE EMPLOYING THREE LAYER METAL INTERCONNECT
    22.
    发明公开
    FLASH MEMORY ARCHITECTURE EMPLOYING THREE LAYER METAL INTERCONNECT 有权
    的闪存架构使用复合式金属连接

    公开(公告)号:EP1256116A2

    公开(公告)日:2002-11-13

    申请号:EP00948688.7

    申请日:2000-07-14

    CPC classification number: G11C8/12 G11C8/10

    Abstract: The present invention discloses a memory wordline decoder that includes plurality of pre-decoded address lines that are electrically connected with a global x-decoder. A sub x-decoder is electrically connected with the global x-decoder for receiving electrical control signals from the global x-decoder. A memory sector is electrically connected with the sub x-decoder. The global x-decoder selectively controls the sub x-decoder to select a plurality of wordlines in the memory sector. A vertical x-decoder is electrically connected with the global x-decoder and the sub x-decoder. The vertical x-decoder is used to select a predetermined wordline by the global x-decoder during operation.

    FLASH MEMORY WORDLINE TRACKING ACROSS WHOLE CHIP
    23.
    发明公开
    FLASH MEMORY WORDLINE TRACKING ACROSS WHOLE CHIP 有权
    快闪存储器的字线信号保持AROUND免费芯片损失

    公开(公告)号:EP1226586A1

    公开(公告)日:2002-07-31

    申请号:EP00967094.4

    申请日:2000-09-29

    CPC classification number: G11C16/08 G11C8/08 G11C8/14

    Abstract: A wordline tracking structure for use in an array of Flash EEPROM memory cells is provided. The tracking structure serves to match reference and sector core wordline voltages across the entire chip regardless of sector location. The tracking structure includes a second VPXG conductor line (422) operatively connected between sector wordlines of a 'far' sector and a reference cell mini-array. The second VPXG conductor line has a substantially smaller time constant than in a first VPXG conductor line (421) operatively connected between an output of a boosting circuit and the sector wordline of the 'far' sector. As a consequence, the reference wordlines voltage associated with the reference cell mini-array will track closely the sector wordline voltage during the read operation regardless of the location of the selected sector.

Patent Agency Ranking