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    ERASING AND PROGRAMMING AN ORGANIC MEMORY DEVICE AND METHODS OF OPERATING AND FABRICATING
    2.
    发明申请
    ERASING AND PROGRAMMING AN ORGANIC MEMORY DEVICE AND METHODS OF OPERATING AND FABRICATING 审中-公开
    擦除和编程有机存储器件及其操作和制作方法

    公开(公告)号：WO2004102579A1

    公开(公告)日：2004-11-25

    申请号：PCT/US2004/011811

    申请日：2004-04-16

    Applicant: ADVANCED MICRO DEVICES, INC. ,  LAN, Zhida ,  BILL, Colin, S. ,  VANBUSKIRK, Michael, A.

    Inventor： LAN, Zhida ,  BILL, Colin, S. ,  VANBUSKIRK, Michael, A.

    IPC: G11C13/02

    CPC classification number: G11C13/0014 ,  B82Y10/00 ,  G11C11/5664 ,  G11C13/0009 ,  G11C13/0016 ,  G11C2213/15 ,  G11C2213/56 ,  G11C2213/71

    Abstract: An organic memory cell (100, 1300, 1500) made of two electrodes (104, 110, 1304, 1306, 1502, 1504) with a selectively conductive media (106/108, 1308) between the two electrodes (104, 110, 1304, 1306, 1502, 1504) is disclosed. The selectively conductive media (106/108, 1308) contains an organic layer (108, 300, 400, 500) and passive layer (106, 200). The selectively conductive media (106/108, 1308) is programmed by applying bias voltages that program a desired impedance state (1301, 1302, 1303) for a memory cell (100, 1300, 1500). The desired impedance state (1301, 1302, 1303) represents one or more bits of information and the memory cell (100, 1300, 1500) does not require constant power or refresh cycles to maintain the desired impedance state. Furthermore, the selectively conductive media (106/108, 1308) is read by applying a current and reading the impedance of the media (106/108, 1308) in order to determine the impedance state (1301, 1302, 1303) of the memory cell (100, 1300, 1500). Methods of making the organic memory devices/cells (100, 1300, 1500), methods of using the organic memory devices/cells (100, 1300, 1500), and devices such as computers containing the organic memory devices/cells (100, 1300, 1500) are also disclosed.

    Abstract translation: 由两个电极（104,110,1304,1306,1502,1504）制成的有机存储单元（100,1300,1500）在两个电极（104,110,1304）之间具有选择性导电介质（106/108,1308） ，1306,1502,1504）。 选择性导电介质（106/108,1308）包含有机层（108,300,400,500）和无源层（106,200）。 选择性导电介质（106/108,1308）通过施加用于存储单元（100,1300,1500）编程期望的阻抗状态（1301,1301,1303）的偏压来编程。 期望的阻抗状态（1301,1301,1303）表示一个或多个信息位，并且存储单元（100,1300,1500）不需要恒定的功率或刷新周期来保持所需的阻抗状态。 此外，通过施加电流并读取介质（106/108,1308）的阻抗来读取选择性导电介质（106/108,1308），以便确定存储器的阻抗状态（1301,1301,1303） 细胞（100,1300,1500）。 制造有机存储器件/单元（100,1300,1500）的方法，使用有机存储器件/单元（100,1300,1500）的方法以及诸如包含有机存储器件/单元（100,1300）的计算机 ，1500）也被公开。

    POLYMER-BASED TRANSISTOR DEVICES, METHODS, AND SYSTEMS
    3.
    发明申请
    POLYMER-BASED TRANSISTOR DEVICES, METHODS, AND SYSTEMS 审中-公开
    基于聚合物的晶体管器件，方法和系统

    公开(公告)号：WO2007064334A1

    公开(公告)日：2007-06-07

    申请号：PCT/US2005/043788

    申请日：2005-12-02

    Applicant: ADVANCED MICRO DEVICES, INC. ,  BILL, Colin, S. ,  VANBUSKIRK, Michael, A. ,  LAN, Zhida ,  ENNALS, John, S. ,  FANG, Tzu-Ning

    Inventor： BILL, Colin, S. ,  VANBUSKIRK, Michael, A. ,  LAN, Zhida ,  ENNALS, John, S. ,  FANG, Tzu-Ning

    IPC: H01L51/05 ,  H01L29/786

    CPC classification number: H01L51/0512 ,  H01L51/0508

    Abstract: Disclosed is a semiconductor transistor device (100) with an annular gate (118) surrounding, at least in part, a channel (110) that conducts current between a first (104) and second (114) source/drain. Also disclosed is a semiconductor transistor device (100) having an annular gate (118) and containing a channel (110) composed of a polymer material. Yet also disclosed is the fabrication of a device utilizing a polymer channel (110) surrounded, at least in part, by an annular gate (118). Further disclosed is a system with a means to control (and/or amplify) current via an annular gate (118) surrounding a channel (110) which conducts current between a first (104) and second (114) source/drain.

    Abstract translation: 公开了具有环形栅极（118）的半导体晶体管器件（100），该环形栅极至少部分地围绕在第一（104）和第二（114）源极/漏极之间传导电流的沟道（110）。 还公开了具有环形栅极（118）并且包含由聚合物材料构成的沟道（110）的半导体晶体管器件（100）。 还公开了使用至少部分由环形栅极（118）包围的聚合物通道（110）的装置的制造。 还公开了一种具有通过围绕在第一（104）和第二（114）源极/漏极之间传导电流的沟道（110）的环形栅极（118）来控制（和/或扩大）电流的装置的系统。

    CONTROL OF MEMORY ARRAYS UTILIZING ZENER DIODE-LIKE DEVICES
    5.
    发明申请
    CONTROL OF MEMORY ARRAYS UTILIZING ZENER DIODE-LIKE DEVICES 审中-公开
    使用ZENER二极管器件控制存储器阵列

    公开(公告)号：WO2004042738A1

    公开(公告)日：2004-05-21

    申请号：PCT/US2003/021680

    申请日：2003-07-10

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： VANBUSKIRK, Michael, A. ,  FANG, Tzu-Ning ,  BILL, Colin, S. ,  LAN, Zhida

    IPC: G11C16/02

    CPC classification number: G11C13/0014 ,  B82Y10/00 ,  G11C11/5664 ,  G11C13/0016 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

    Abstract: The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array (100, 200, 212, 300, 400). State change voltages can be applied to a single device in the array (100, 200, 212, 300, 400) of semiconductor devices without the need for transistor-type voltage controls. The diodic effect (114, 508, 510, 900, 1014, 1114, 1214, 1502, 1702, 1812) of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.

    Abstract translation: 本发明通过辅助单个器件改变半导体阵列（100,200,212,300,400）中的状态的方式来有助于半导体器件。 可以将状态变化电压施加到半导体器件的阵列（100,200,212,300,400）中的单个器件，而不需要晶体管型电压控制。 本发明的二体效应（114,508,510,910,1014,1114,1214,1502,1702,1812）通过允许状态改变所需的特定电压水平仅发生在期望的装置来促进这种活动。 以这种方式，可以在不利用晶体管技术的情况下用不同的数据或状态对器件阵列进行编程。 本发明还允许制造这些类型的器件的非常有效的方法，消除了制造昂贵的外部电压控制半导体器件的需要。

    BUILT-IN-SELF-TEST OF FLASH MEMORY CELLS
    6.
    发明申请
    BUILT-IN-SELF-TEST OF FLASH MEMORY CELLS 审中-公开
    闪存存储器内部自检

    公开(公告)号：WO2004010437A1

    公开(公告)日：2004-01-29

    申请号：PCT/US2003/018309

    申请日：2003-06-10

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： BILL, Colin, S. ,  HALIM, Azrul ,  HAMILTON, Darlene ,  BAUTISTA, Edward, V., Jr. ,  LEE, Weng, Fook ,  CHEAH, Ken, Cheong ,  LAW, Chee, Boon ,  TEH, Boon, Tang ,  KUCERA, Joseph ,  SALLEH, Syahrizal

    IPC: G11C29/00

    CPC classification number: G11C29/72 ,  G11C16/04 ,  G11C29/16 ,  G11C29/44 ,  G11C29/48

    Abstract: In a BIST (built-in-self-test) system (300) for testing flash memory cells (304) fabricated on a semiconductor substrate (302), a BIST (built-in-self-test) interface (312), a front-end state machine (314), and a back-end state machine (316) are fabricated on the semiconductor substrate (302). The BIST interface (312) inputs test mode data from an external test system (318), and the front-end state machine (314) decodes the test mode data to determine an order for performing at least one desired test mode. The back-end state machine (316) performs the at least one desired test mode on the flash memory cells (304) according to the order for on-­chip testing of the flash memory cells (304).

    Abstract translation: 在用于测试制造在半导体衬底（302）上的闪存单元（304）的BIST（内置自测试）系统（300）中，BIST（内置自检）接口（312）， 前端状态机（314）和后端状态机（316）制造在半导体衬底（302）上。 BIST接口（312）从外部测试系统（318）输入测试模式数据，并且前端状态机（314）解码测试模式数据，以确定执行至少一个所需测试模式的顺序。 后端状态机（316）根据闪速存储器单元（304）的片上测试顺序在闪速存储单元（304）上执行至少一个期望的测试模式。

    EFFICIENT PAGE MODE WRITE CIRCUITRY FOR E2PROMS
    7.
    发明申请
    EFFICIENT PAGE MODE WRITE CIRCUITRY FOR E2PROMS 审中-公开
    E <2>项目的有效页面模式写入电路

    公开(公告)号：WO1986004727A1

    公开(公告)日：1986-08-14

    申请号：PCT/US1986000222

    申请日：1986-01-30

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： ADVANCED MICRO DEVICES, INC. ,  BRINER, Michael, S. ,  BILL, Colin, S. ,  SUCIU, Paul ,  RINERSON, Darrell

    IPC: G11C11/40

    CPC classification number: G11C16/10 ,  G11C2216/14

    Abstract: A page mode write system for an E PROM array including active latches (48) for storing loaded data on bit lines (14), independent bit line grounds (28) for isolating the cells (8) in a byte (40), and program gate lines (38) in each byte (40) for tagging those bytes (40) that will undergo a charge/discharge cycle during the write cycle.

    Abstract translation: 一种用于E 2 PROM阵列的页面模式写入系统，包括用于在位线（14）上存储加载的数据的有源锁存器（48），用于隔离字节（40）中的单元（8）的独立位线接地（28） ，以及每个字节（40）中的编程门线（38），用于标记在写周期期间将经历充电/放电循环的那些字节（40）。

    TRIMMING METHOD AND SYSTEM FOR WORDLINE BOOSTER TO MINIMIZE PROCESS VARIATION OF BOOSTED WORDLINE VOLTAGE
    8.
    发明公开
    TRIMMING METHOD AND SYSTEM FOR WORDLINE BOOSTER TO MINIMIZE PROCESS VARIATION OF BOOSTED WORDLINE VOLTAGE 有权
    电路及方法微调，字线驱动器和最小化生产相关的各种变化INCREASED字线电压

    公开(公告)号：EP1266382A1

    公开(公告)日：2002-12-18

    申请号：EP01910464.5

    申请日：2001-02-07

    Applicant: ADVANCED MICRO DEVICES INC.

    Inventor： BILL, Colin, S. ,  GUTALA, Ravi, P.

    IPC: G11C16/08 ,  G11C8/00 ,  G11C5/14

    CPC classification number: G11C16/08 ,  G11C5/145 ,  G11C8/08

    Abstract: A method and system for controlling a boosted wordline voltage that is used during a read operation in a flash memory (10) is disclosed by the present invention. In the preferred embodiment, a gate voltage is generated by a voltage booster (48) in a wordline voltage booster circuit (20). An adjustable clamp circuit (12) is electrically connected with the wordline voltage booster circuit (20) for clamping the gate voltage that is generated by the voltage booster (48) at a predetermined voltage level. The predetermined voltage level may be adjusted with a trimming circuit (14) that is electrically connected to the adjustable clamp circuit (12), depending on process variations experienced during fabrication by the adjustable clamp circuit (12).

    REFERENCE CELL TRIMMING VERIFICATION CIRCUIT
    10.
    发明授权
    REFERENCE CELL TRIMMING VERIFICATION CIRCUIT 有权
    测试电路进行微调参考单元

    公开(公告)号：EP1264315B1

    公开(公告)日：2003-09-10

    申请号：EP01920327.2

    申请日：2001-03-12

    Applicant: ADVANCED MICRO DEVICES INC.

    Inventor： PAN, Feng ,  BILL, Colin, S.

    IPC: G11C29/00 ,  G11C16/34

    CPC classification number: G11C16/3459 ,  G11C16/3454

    Abstract: A reference trimming verify circuit and method is provided for performing a program verify operation on a reference cell transistor in an array of Flash EEPROM memory cells. A reference current branch (14) is used to generate a reference current corresponding to a predetermined overdrive voltage of the reference cell to be programmed. A drain current branch (16) is coupled to the reference cell transistor to be programmed and generates a drain current at a fixed gate voltage applied to its control gate and at a predetermined drain voltage applied to its drain when the drain current is at the desired level. A comparator (18) is used to compare a sensed voltage corresponding to the drain current and a reference voltage corresponding to the reference current. The comparator generates an output signal which is at a low logic level when the sensed voltage is less than the reference voltage and which is at a high logic level when the sensed voltage is greater than the reference voltage. A program pulse is applied to the reference transistor each time the comparator generates the low logic level and terminates the program pulse when the comparator generates the high logic level.

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