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公开(公告)号：CA2408252A1
公开(公告)日：1994-07-07
申请号：CA2408252
申请日：1993-12-16
Applicant: APPLE COMPUTER
Inventor： OPRESCU FLORIN
IPC: G06F13/368 , G06F13/00 , G06F13/36 , G06F13/362 , G06F13/40 , G06F13/42 , G06F15/16 , G06F15/173 , G06F15/177 , H04L12/40 , H04L12/44 , H04L12/56 , H04L12/64
Abstract: A bus arbitration scheme is implemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph. The hierarchical arrangement of nodes has one node designated a root while all other modes have established parent-child relationships with the nodes to which they are linked. Each node may have a plurality of connected child ports with a predetermined acknowledgment priority scheme established. Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus. The root node may always assert its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer. Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme. Preemptive bus initialization may be triggered by any node upon detection of a necessitating error or addition or removal of a connection to an existing node.
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公开(公告)号：CA2151369A1
公开(公告)日：1994-07-07
申请号：CA2151369
申请日：1993-12-16
Applicant: APPLE COMPUTER
Inventor： OPRESCU FLORIN
IPC: G06F13/368 , G06F13/00 , G06F13/36 , G06F13/362 , G06F13/40 , G06F13/42 , G06F15/16 , G06F15/173 , G06F15/177 , H04L12/40 , H04L12/44 , H04L12/56 , H04L12/64
Abstract: A bus arbitration scheme is implemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph. The hierarchical arrangement of nodes has one node designated a root while all other nodes have established parent/child relationships with the nodes to which they are linked. Each node may have a plurality of connected child ports with a predetermined acknowledgment priority scheme established. Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus. The root node may always assert its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer. Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme. Preemptive bus initialization may be triggered by any node upon detection of a necessitating error or addition or removal of a connection to an existing node.
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公开(公告)号：DE69334171D1
公开(公告)日：2007-10-25
申请号：DE69334171
申请日：1993-12-16
Applicant: APPLE COMPUTER
Inventor： OPRESCU FLORIN
IPC: G06F13/368 , G06F15/16 , G06F13/00 , G06F13/36 , G06F13/362 , G06F13/40 , G06F13/42 , G06F15/173 , G06F15/177 , H04L12/40 , H04L12/44 , H04L12/56 , H04L12/64
Abstract: A bus arbitration scheme is implemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph. The hierarchical arrangement of nodes has one node designated a root while all other nodes have established parent/child relationships with the nodes to which they are linked. Each node may have a plurality of connected child ports with a predetermined acknowledgement priority scheme established. Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus. The root node may always asserts its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer. Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme. Preemptive bus initilialization may be triggered by any node upon detection of a necessitating error or addition or removal of a connection to an existing node.
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公开(公告)号：DE69333798D1
公开(公告)日：2005-06-02
申请号：DE69333798
申请日：1993-12-16
Applicant: APPLE COMPUTER
Inventor： OPRESCU FLORIN
IPC: G06F13/368 , G06F13/00 , G06F13/36 , G06F13/362 , G06F13/40 , G06F13/42 , G06F15/16 , G06F15/173 , G06F15/177 , H04L12/40 , H04L12/44 , H04L12/56 , H04L12/64
Abstract: A bus arbitration scheme is implemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph. The hierarchical arrangement of nodes has one node designated a root while all other nodes have established parent/child relationships with the nodes to which they are linked. Each node may have a plurality of connected child ports with a predetermined acknowledgement priority scheme established. Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus. The root node may always asserts its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer. Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme. Preemptive bus initilialization may be triggered by any node upon detection of a necessitating error or addition or removal of a connection to an existing node.
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公开(公告)号：DE69332804T2
公开(公告)日：2004-02-05
申请号：DE69332804
申请日：1993-12-16
Applicant: APPLE COMPUTER
Inventor： VAN BRUNT ROGER , OPRESCU FLORIN
IPC: G06F13/378 , G06F13/40 , H03K19/0175 , H03M5/16 , H03M5/18 , H04L25/02 , H04L25/49
Abstract: The present invention provides a method and apparatus for transmitting NRZ data signals across an interface comprising an isolation barrier disposed between two devices interconnected via a bus. The apparatus comprises a signal differentiator for receiving an NRZ data signal and outputting a differentiated signal. A driver comprising a tri-state gate has a first input the data signal and as a second input the differentiated signal for enabling the tri-state gate when the differentiated signal is high. A bias voltage is applied to an output of the tri-state gate to derive as output a transmission signal for transmission via the bus across the interface between the two devices. In this way, the transmission signal output from the first device comprises an intermediate transmission signal corresponding to the bias voltage when the tri-state gate is disabled, a height transmission signal when the tri-state gate is enabled and the first input to the tri-state gate is high, and a low transmission signal when the tri-state gate is enabled and the first input to the tri-state gate is low. A Schmidt trigger is provided as a receiver in the second device for receiving an input the transmission signal and outputting a reconstituted data signal corresponding to the synchronized data signal.
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Patent Agency Ranking
公开(公告)号：DE69332778D1
公开(公告)日：2003-04-24
申请号：DE69332778
申请日：1993-12-16
Applicant: APPLE COMPUTER
Inventor： OPRESCU FLORIN
IPC: G06F15/16 , G06F13/00 , G06F13/14 , G06F13/36 , G06F13/362 , G06F13/40 , G06F15/173 , G06F15/177 , H04L12/40 , H04L12/44 , H04L12/56 , H04L12/64 , H04L29/12
Abstract: A node identification system is described for use in a computer system in which the various components of the system are interconnected via nodes on a communications bus. Once the topology of the nodes has been resolved into an acyclic directed graph, each node may be assigned a non-predetermined unique address. Each node having a plurality of ports has an apriori assigned priority for port selection. Each child node connected to a parent is allowed to respond in the predetermined sequence depending upon the port through which it is connected to its parent. Each node in the graph will announce its presence according to its location in the graph. Each receives an address incremented from the previous addresses assigned, thereby insuring uniqueness. The same mechanism may be implemented to allow each node in turn to broadcast information on the bus concerning the parameters of its local host. Likewise, additional information may be conveyed from each node concerning connections to other nodes thereby allowing a host system to generate a map of the resolved topology including any information about disabled links which may be used for redundancy purposes.
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公开(公告)号：DE69429508T2
公开(公告)日：2002-07-18
申请号：DE69429508
申请日：1994-03-11
Applicant: APPLE COMPUTER
Inventor： OPRESCU FLORIN , VAN BRUNT ROGER
Abstract: The present invention provides a bus transceiver incorporating a high speed, binary transfer mode for the half-duplex transfer of data signals with a ternary control transfer mode having a full duplex dominant logic transmission scheme for the full duplex transfer of control signals. In one embodiment of the present invention, the above-noted transfer modes are implemented in a bus architecture which includes at least a first communications node coupled to a second communications node via a twisted pair, serial bus. Each node comprises first transceiver and second transceivers having a differential driver for driving on the bus signal states comprising first and second signal states having equal current amplitudes opposite in sign and a third signal state having approximately a zero current amplitude, a high speed binary receiver for receiving high speed data signals during data transfer phases and a ternary receiver for receiving control signals during control transfer phases. The ternary receiver comprises two binary receivers for detecting resultant current amplitudes created on the bus during simultaneous driving of control signals by the nodes during the control transfer phases and logic means for combining the resultant current amplitudes on the bus with the signal states driven by the local transceiver to output reconstructed control signals representing the control signals driven on the bus by the corresponding transceiver. Furthermore, both transceivers further include a preemptive signaling receiver for the detection of preemptive control messages which act to terminate the data transfer phases upon receipt of the message so that higher priority control transfers may take place.
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公开(公告)号：AU2101995A
公开(公告)日：1995-10-23
申请号：AU2101995
申请日：1995-03-22
Applicant: APPLE COMPUTER
Inventor： BRUNT ROGER VAN , OPRESCU FLORIN
Abstract: The level shifter provides a selective voltage level shift to a common mode signal level on a twisted pair signal line. The level shift is selectively performed based upon the input level of the common mode voltage. The level shifter is advantageously employed in a low voltage circuit wherein lacking sufficient voltage head room to accommodate a constant common mode level shift. An exemplary embodiment is described wherein the level shifter is employed within a bus transceiver of a bus system employing IEEE P1394 bus protocol. In the exemplary embodiment, the selective level shift is applied only to bus signals occurring during an idle phase and an arbitration phase, with no level shift performed during a data phase.
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公开(公告)号：AU7315494A
公开(公告)日：1995-01-17
申请号：AU7315494
申请日：1994-06-21
Applicant: APPLE COMPUTER
Inventor： BRUNT ROGER W VAN , OPRESCU FLORIN
IPC: G06F13/40 , H04L12/40 , H04L12/413
Abstract: A bus circuit for implementing a high speed dominant logic bus for a differential signal. The bus circuit is useful in a communication network having a plurality of multi-port nodes that are coupled by point-to-point links that communicate differential signals. Each port in the node includes a bus driver that receives the differential signal received at the port. The bus driver supplies a differential current signal to a first bus. A terminator circuit is coupled to the first differential bus, to receive the differential current signals supplied from the ports. The terminator circuit, responsive to the differential current signal, outputs a differential voltage signal indicative of either a dominant state or a non-dominant state to a second differential bus, which is coupled to the plurality of ports for transmission. A biasing circuit for the bus drivers allows operation at low voltages, and furthermore insures that the zero crossing of crossing of the differential voltage signal on the second differential bus.
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公开(公告)号：AU6445494A
公开(公告)日：1994-10-11
申请号：AU6445494
申请日：1994-03-11
Applicant: APPLE COMPUTER
Inventor： OPRESCU FLORIN , BRUNT ROGER VAN
Abstract: The present invention provides a bus transceiver incorporating a high speed, binary transfer mode for the half-duplex transfer of data signals with a ternary control transfer mode having a full duplex dominant logic transmission scheme for the full duplex transfer of control signals. In one embodiment of the present invention, the above-noted transfer modes are implemented in a bus architecture which includes at least a first communications node coupled to a second communications node via a twisted pair, serial bus. Each node comprises first transceiver and second transceivers having a differential driver for driving on the bus signal states comprising first and second signal states having equal current amplitudes opposite in sign and a third signal state having approximately a zero current amplitude, a high speed binary receiver for receiving high speed data signals during data transfer phases and a ternary receiver for receiving control signals during control transfer phases. To permit the receivers of the present invention to receive the transmitted signals at the amplitude required to detect the proper bus voltage values, the present invention further provides a means for common mode shifting of the signals at the front end of the receivers while providing for a voltage offset independent of the fabrication process. This common mode shifting means also permits the implementation of a single ternary receiver in place of each of the binary, ternary and preemptive signaling receivers for each transceiver. In this manner, the present invention can be modified so that both transfer modes in addition to the preemptive signaling method can be performed using a single ternary receiver.
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