-
公开(公告)号：AU2104495A
公开(公告)日：1995-10-23
申请号：AU2104495
申请日：1995-03-21
Applicant: APPLE COMPUTER
Inventor： BRUNT ROGER W VAN , OPRESCU FLORIN A
Abstract: A mechanism and method for efficiently communicating information regarding particular communication rate ("speed signal") between two or more communication stations (of a communication network). The transmitter operates on the IEEE P1394 High Performance Serial Bus to supply both differential and common mode signaling required by the IEEE standard for exemplary data transfer rates of 100 and 200 Mbit transmission. The present invention includes a transmission circuit that may operate in a differential signal mode and simultaneously in a common mode signal mode both utilizing a twisted pair cable. Data may be transmitted on the twisted pair at small differential signals. Information regarding the signal speed between two coupled units may be simultaneously transmitted using variations in the common mode voltage over the twisted pair. Communication may be initiated at a slower communication rate and then upgraded as appropriate for the two units. The present invention allows an efficient single circuit mechanism for communication units to transmit differential data and also to signal the use of a high speed communication rate with a common mode voltage. The present invention is especially useful within networks having units of varying versions and signal transfer rates.
-
Patent Agency Ranking
公开(公告)号：AU1968895A
公开(公告)日：1995-09-11
申请号：AU1968895
申请日：1995-02-23
Applicant: APPLE COMPUTER
Inventor： BRUNT ROGER W VAN , OPRESCU FLORIN A
IPC: H03K5/1252 , H03F3/45 , H03K5/02 , H03K5/08 , H03K5/24 , H03K19/0175 , H04L25/02
-
公开(公告)号：AU7315494A
公开(公告)日：1995-01-17
申请号：AU7315494
申请日：1994-06-21
Applicant: APPLE COMPUTER
Inventor： BRUNT ROGER W VAN , OPRESCU FLORIN
IPC: G06F13/40 , H04L12/40 , H04L12/413
Abstract: A bus circuit for implementing a high speed dominant logic bus for a differential signal. The bus circuit is useful in a communication network having a plurality of multi-port nodes that are coupled by point-to-point links that communicate differential signals. Each port in the node includes a bus driver that receives the differential signal received at the port. The bus driver supplies a differential current signal to a first bus. A terminator circuit is coupled to the first differential bus, to receive the differential current signals supplied from the ports. The terminator circuit, responsive to the differential current signal, outputs a differential voltage signal indicative of either a dominant state or a non-dominant state to a second differential bus, which is coupled to the plurality of ports for transmission. A biasing circuit for the bus drivers allows operation at low voltages, and furthermore insures that the zero crossing of crossing of the differential voltage signal on the second differential bus.
-
公开(公告)号：AU2105295A
公开(公告)日：1995-10-17
申请号：AU2105295
申请日：1995-03-21
Applicant: APPLE COMPUTER
Inventor： BRUNT ROGER W VAN , OPRESCU FLORIN A
Abstract: In a driver circuit for a twisted pair cable, a compensator for preventing appreciable common mode current flow into or out of the twisted pair cable in response to the device receiving a wide range of common mode voltage bias levels. A wide range of external bias voltages may be received as a result of variations in the ground node voltages of two coupled devices. The compensator circuit utilizes a feed back loop and monitors the bias voltage received on the twisted pair cable. As the magnitude of the common mode current increases due to external bias voltage variation from a reference bias voltage, the current flow of p-channel transistors, coupled in an arrangement of the present invention, is increased (or decreased, as necessary) so that reduced common mode current flows onto the twisted pair cable. The present invention reduces appreciable common mode current flow through the twisted pair cable from the driver that are due to variations in the external bias voltage between communication devices. The present invention provides high common mode output impedance for the driver circuit by altering the effective common mode common mode early voltage characteristics of the driver circuit while utilizing shorter channel length transistors for high speed communication capacity. The present invention also offers reduced current supply capacity of the common mode bias voltage source. The present invention operates ideally within driver circuits compatible with the IEEE P1394 communication standard.
-
5.发明专利
公开(公告)号：AU6359694A
公开(公告)日：1994-09-26
申请号：AU6359694
申请日：1994-03-04
Applicant: APPLE COMPUTER
Inventor： OPRESCU FLORIN , BRUNT ROGER W VAN
Abstract: A bus interconnect device including port control logic for a communication network having a plurality of multi-port nodes that are connected with point-to-point links. Each node includes a transceiver, turn around logic that controls the transceiver, and a dominant logic physical bus that is coupled to all ports in a node. A bus interconnect device includes a first port, a second port, and a point-to-point link between the first and second ports. During arbitration, from the viewpoint of each node, the bus interconnect devices cause the plurality of physical buses to appear to be a single logical bus having a dominant logic. During data transfer following arbitration, the bus interconnect devices are configured to transmit data from the winning node to all other nodes.
-
公开(公告)号：AU6163894A
公开(公告)日：1994-08-15
申请号：AU6163894
申请日：1994-01-12
Applicant: APPLE COMPUTER
Inventor： OPRESCU FLORIN , BRUNT ROGER W VAN
Abstract: A node for a communication system that has a plurality of nodes, each of which may be coupled to a local host. The nodes are coupled between themselves in a tree topology by a plurality of point-to-point links. The interconnected nodes provide a first bus configuration for arbitration like a single bus. Following arbitration, the interconnected nodes provide a second configuration for high speed unidirectional data transfer without the bandwidth limitations of a single bus. Each node includes an arbiter, a data bus, a plurality of ports, a first multiplexer to select either the arbiter or the data bus, and a second multiplexer to select either the arbiter or the data bus. The data bus includes a transmit bus and a receive bus that are coupled with a repeater circuit that can resynchronize the data. During arbitration, the multiplexers select the arbiter to provide the function of a single bus for all the nodes. During data transfer, the multiplexers are configured for transmission of data. Furthermore, a node can function as a repeater and resynchronizer even if it is not connected to a local host or if the local host is turned off or otherwise nonoperational.
-
-
-
-
-
Search Results
6
records
(took 0.031 seconds)
