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    DISPLAY PIPE ALTERNATE CACHE HINT
    21.
    发明申请
    DISPLAY PIPE ALTERNATE CACHE HINT 审中-公开
    显示管替代缓存提示

    公开(公告)号：WO2014043063A1

    公开(公告)日：2014-03-20

    申请号：PCT/US2013/058881

    申请日：2013-09-10

    Applicant: APPLE INC.

    Inventor： TRIPATHI, Brijesh ,  HOLLAND, Peter F.

    IPC: G09G5/39 ,  G09G5/00

    CPC classification number: G06F12/0888 ,  G06F2212/455 ,  G09G5/001 ,  G09G5/363 ,  G09G5/39 ,  G09G5/395 ,  G09G2360/121 ,  G09G2360/123

    Abstract: A system and method for efficiently allocating data in a memory hierarchy. A system includes a memory controller for controlling accesses to a memory and a display controller for processing video frame data. The memory controller includes a cache capable of storing data read from the memory. A given video frame may be processed by the display controller and presented on a respective display screen. During processing, control logic within the display controller sends multiple memory access requests to the memory controller with cache hint information. For the frame data, the cache hint information may alternate between (i) indicating to store frame data read in response to respective requests in the memory cache and (ii) indicating to not store the frame data read in response to respective requests in the memory cache.

    Abstract translation: 一种用于在存储器层级中有效分配数据的系统和方法。 系统包括用于控制对存储器的访问的存储器控​​制器和用于处理视频帧数据的显示控制器。 存储器控制器包括能够存储从存储器读取的数据的高速缓存器。 给定的视频帧可以由显示控制器处理并呈现在相应的显示屏幕上。 在处理期间，显示控制器内的控制逻辑使用高速缓存提示信息向存储器控制器发送多个存储器访问请求。 对于帧数据，缓存提示信息可以在（i）指示存储响应于存储器高速缓存中的相应请求而读取的帧数据和（ii）指示不存储响应于存储器中的各个请求而读取的帧数据的交替 缓存。

    EXTENDED RANGE COLOR SPACE
    22.
    发明申请
    EXTENDED RANGE COLOR SPACE 审中-公开
    扩展范围的颜色空间

    公开(公告)号：WO2013130303A1

    公开(公告)日：2013-09-06

    申请号：PCT/US2013/026702

    申请日：2013-02-19

    Applicant: APPLE INC.

    Inventor： TRIPATHI, Brijesh ,  OKRUHLICA, Craig M. ,  HARPER, John S. ,  SWEN, Steve

    IPC: G09G5/02 ,  G06K9/00 ,  G06K9/40

    CPC classification number: H04N9/68

    Abstract: Techniques are disclosed relating to additive color systems. In one embodiment, an apparatus is disclosed that includes a device configured to operate on pixel data having color component values falling within an extended range outside of 0.0 to 1.0 corresponding to an extended range color space. In one embodiment, a gamma correction function is disclosed that can be applied to the pixel data, where the gamma correction function is applicable to both negative and positive values. Various embodiments of formats for arranging pixel data are also disclosed.

    Abstract translation: 公开了与加色系统有关的技术。 在一个实施例中，公开了一种装置，其包括被配置为对具有落在与扩展范围颜色空间相对应的0.0至1.0之外的扩展范围内的颜色分量值的像素数据进行操作的装置。 在一个实施例中，公开了可以应用于像素数据的伽马校正功能，其中伽马校正功能适用于负值和正值两者。 还公开了用于布置像素数据的格式的各种实施例。

    PARALLEL SCALER PROCESSING
    23.
    发明申请
    PARALLEL SCALER PROCESSING 审中-公开
    并行扩展器处理

    公开(公告)号：WO2013126330A1

    公开(公告)日：2013-08-29

    申请号：PCT/US2013/026672

    申请日：2013-02-19

    Applicant: APPLE INC.

    Inventor： TRIPATHI, Brijesh ,  BHARGAVA, Nitin ,  OKRUHLICA, Loop

    IPC: G06K9/32

    CPC classification number: G06T3/4007

    Abstract: A parallel scaler unit for simultaneously scaling multiple pixels from a source image. The scaler unit includes multiple vertical scalers and multiple horizontal scalers. A column of pixels from the source image is presented to the vertical scalers, and each vertical scaler selects appropriate pixels from the column of pixels for scaling. Each vertical scaler scales the selected pixels in a vertical direction and then conveys the vertically scaled pixels to a corresponding horizontal scaler. Each horizontal scaler scales the received pixels in a horizontal direction.

    Abstract translation: 一个并行缩放器单元，用于同时缩放源图像中的多个像素。 缩放器单元包括多个垂直缩放器和多个水平缩放器。 来自源图像的一列像素被呈现给垂直缩放器，并且每个垂直缩放器从用于缩放的像素列中选择合适的像素。 每个垂直缩放器在垂直方向上缩放所选择的像素，然后将垂直缩放的像素传送到相应的水平缩放器。 每个水平缩放器在水平方向上缩放接收到的像素。

    AGILE CLOCKING WITH RECEIVER PLL MANAGEMENT
    24.
    发明申请
    AGILE CLOCKING WITH RECEIVER PLL MANAGEMENT 审中-公开
    具有接收器PLL管理的AGILE时钟

    公开(公告)号：WO2013074200A1

    公开(公告)日：2013-05-23

    申请号：PCT/US2012/056857

    申请日：2012-09-24

    Applicant: APPLE INC. ,  TRIPATHI, Brijesh ,  MILLET, Timothy J.

    Inventor： TRIPATHI, Brijesh ,  MILLET, Timothy J.

    IPC: H04N5/05

    CPC classification number: G06F1/08 ,  H04B15/06

    Abstract: A method and apparatus for changing a frequency of a clock signal to avoid interference is disclosed. In one embodiment, data conveyed on a first interface is synchronized to a clock signal at a first frequency. Signals are conveyed on a second interface at another frequency. Responsive to a change of the frequency at which signals are conveyed on a second interface, a clock control unit associated with the first interface initiates a change of the clock signal to a second frequency. The second frequency may be chosen as to not cause interference with the frequency at which signals are conveyed on the second interface. The change of the clock frequency may be performed in such a manner as to prevent spurious activity on the clock line of the interface.

    Abstract translation: 公开了一种用于改变时钟信号的频率以避免干扰的方法和装置。 在一个实施例中，在第一接口上传送的数据与第一频率的时钟信号同步。 信号在另一个频率的第二个接口上传送。 响应于在第二接口上传送信号的频率的变化，与第一接口相关联的时钟控制单元启动时钟信号的变化到第二频率。 第二频率可以被选择为不引起对在第二接口上传送信号的频率的干扰。 时钟频率的改变可以以防止对接口的时钟线的虚假活动的方式来执行。

    CABLE WITH FADE AND HOT PLUG FEATURES
    28.
    发明公开
    CABLE WITH FADE AND HOT PLUG FEATURES 审中-公开
    KABEL MIT AUSBLENDUNGS- UND HOT-PLUG-FUNKTION

    公开(公告)号：EP2805227A1

    公开(公告)日：2014-11-26

    申请号：EP13706788.0

    申请日：2013-02-04

    Applicant: Apple Inc.

    Inventor： SHARMA, Anup K. ,  KRUEGER, Scott P. ,  HOLLABAUGH, James M. ,  YEPEZ, Roberto G. ,  ADLER, Mitchell D. ,  TRIPATHI, Brijesh ,  TERLIZZI, Jeffrey J. ,  TIKALSKY, Terry L.

    IPC: G06F3/14

    CPC classification number: G06F3/1431 ,  G06F3/14 ,  G06F13/385 ,  G06F13/4013 ,  G06F13/4018 ,  G06T1/60 ,  Y02D10/14 ,  Y02D10/151

    Abstract: In an embodiment, a host computing device includes an internal display and also includes a connector to connect to an external display. A cable is provided to connect to the connector and to connect to the external display. The cable includes video processing capabilities. For example, the cable may include a memory configured to store a frame buffer. The frame buffer may store a frame of video data for further processing by the video processing device in the cable. The video processing device may manipulate the frame in a variety of ways, e.g. scaling, rotating, gamma correction, dither correction, etc.

    Abstract translation: 在一个实施例中，主机计算设备包括内部显示器，并且还包括连接到外部显示器的连接器。 提供电缆连接到连接器并连接到外部显示器。 电缆包括视频处理功能。 例如，电缆可以包括被配置为存储帧缓冲器的存储器。 帧缓冲器可以存储视频数据的帧，以便视频处理设备在电缆中进一步处理。 视频处理设备可以以各种方式操纵帧，例如， 缩放，旋转，伽马校正，抖动校正等

    TIMESTAMP BASED DISPLAY UPDATE MECHANISM
    29.
    发明申请
    TIMESTAMP BASED DISPLAY UPDATE MECHANISM 审中-公开
    基于TIMESTAMP的显示更新机制

    公开(公告)号：WO2017058343A1

    公开(公告)日：2017-04-06

    申请号：PCT/US2016/043394

    申请日：2016-07-21

    Applicant: APPLE INC.

    Inventor： TRIPATHI, Brijesh ,  SPENCE, Arthur L. ,  DE CESARE, Joshua P. ,  GARBACEA, Ilie ,  COTE, Guy ,  CHAPPALLI, Mahesh B. ,  GRAY, Malcolm D. ,  TANN, Christopher P.

    IPC: G06F3/147 ,  G06F3/14

    CPC classification number: G09G5/395 ,  G06F3/1407 ,  G06F3/147 ,  G09G2310/08 ,  G09G2340/0407 ,  G09G2340/0464 ,  G09G2360/127

    Abstract: Systems, apparatuses, and methods for implementing a timestamp based display update mechanism. A display control unit includes a timestamp queue for storing timestamps, wherein each timestamp indicates when a corresponding frame configuration set should be fetched from memory. At pre-defined intervals (810), the display control unit may compare the timestamp of the topmost entry of the timestamp queue to a global timer value (815). If the timestamp is earlier than the global timer value (820), the display control unit may pop the timestamp entry and fetch the frame next configuration set from memory (825). The display control unit may then apply the updates of the frame configuration set to its pixel processing elements (835). After applying the updates, the display control unit may fetch and process the source pixel data and then drive the pixels of the next frame to the display (840).

    Abstract translation: 用于实现基于时间戳的显示更新机制的系统，装置和方法。 显示控制单元包括用于存储时间戳的时间戳队列，其中每个时间戳指示何时应当从存储器取出对应的帧配置集。 以预定义的间隔（810），显示控制单元可以将时间戳队列的最上面的条目的时间戳与全局定时器值（815）进行比较。 如果时间戳早于全局定时器值（820），则显示控制单元可以弹出时间戳条目并从存储器提取下一个配置集合（825）。 然后，显示控制单元可以将帧配置集的更新应用于其像素处理元件（835）。 在应用更新之后，显示控制单元可以获取并处理源像素数据，然后将下一帧的像素驱动到显示器（840）。

    UNDER VOLTAGE DETECTION AND PERFORMANCE THROTTLING
    30.
    发明申请
    UNDER VOLTAGE DETECTION AND PERFORMANCE THROTTLING 审中-公开
    在电压检测和性能曲线下

    公开(公告)号：WO2016160229A1

    公开(公告)日：2016-10-06

    申请号：PCT/US2016/020197

    申请日：2016-03-01

    Applicant: APPLE INC.

    Inventor： TRIPATHI, Brijesh ,  SMITH, Eric G. ,  MACHNICKI, Erik P. ,  CHO, Jung Wook ,  ALASHMOUNY, Khaled M. ,  KATTEL, Kiran B. ,  BETTADA, Vijay M. ,  YANG, Bo ,  WEI, Wenlong

    IPC: G01R19/165 ,  G01R19/10 ,  G01R31/28 ,  G01R23/165

    CPC classification number: G05F3/02 ,  G06F1/324 ,  G06F1/3296

    Abstract: An under voltage detection circuit and method of operating an IC including the same is disclosed. In one embodiment, an IC includes an under voltage protection circuit having first and second comparators configured to compare a supply voltage to first and second voltage thresholds, respectively, with the second voltage threshold being greater than the first. A logic circuit is coupled to receive signals from the first and second comparators. During operation in a high performance state by a corresponding functional circuit, the logic circuit is configured to cause assertion of a throttling signal responsive to an indication that the supply voltage has fallen below the first threshold. A clock signal provided to the functional circuit may be throttled responsive to the indication. If the supply voltage subsequently rises to a level above the second threshold, the throttling signal may be de-asserted.

    Abstract translation: 公开了一种欠压检测电路及其运算方法。 在一个实施例中，IC包括欠压保护电路，其具有第一和第二比较器，其被配置为分别将电源电压与第一和第二电压阈值进行比较，其中第二电压阈值大于第一电压阈值。 逻辑电路被耦合以从第一和第二比较器接收信号。 在通过相应的功能电路在高性能状态下操作期间，逻辑电路被配置为响应于电源电压已经低于第一阈值的指示而导致节流信号的断言。 提供给功能电路的时钟信号可以响应于指示而被节流。 如果电源电压随后上升到高于第二阈值的水平，则节流信号可以被取消断言。

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