公开(公告)号：WO2018026709A1

公开(公告)日：2018-02-08

申请号：PCT/US2017/044668

申请日：2017-07-31

Applicant: APPLE INC.

Inventor： GULATI, Manu ,  HOLLAND, Peter F. ,  MACHNICKI, Erik P. ,  JETER, Robert E. ,  NOTANI, Rakesh L. ,  PARIK, Neeraj ,  SCHAUB, Marc A.

IPC: G06F13/16

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0683 ,  G06F13/1673 ,  G11C11/40615

Abstract: In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.

Abstract translation: 在一些实施例中，系统包括存储器系统，实时计算设备和控制器。 实时计算设备将数据存储在具有对应的存储阈值的本地缓冲区内，其中数据满足存储阈值，并且其中存储阈值基于存储器系统的等待时间和预期的数据利用率 本地缓冲区。 控制器检测到存储器系统应当执行操作，其中存储器系统在操作期间对于实时计算设备不可用。 响应于检测到操作的时间量超过对应于存储阈值的时间量，控制器覆盖存储阈值。 控制器可以通过修改存储阈值并且通过超越实时计算设备对存储器系统的访问请求的默认优先级来覆盖存储阈值。

公开(公告)号：WO2014100152A1

公开(公告)日：2014-06-26

申请号：PCT/US2013/076075

申请日：2013-12-18

Applicant: APPLE INC.

Inventor： MACHNICKI, Erik P. ,  SAUND, Gurjeet S. ,  FUKAMI, Munetoshi ,  KEIL, Shane J.

IPC: G06F1/32

CPC classification number: G05B11/01 ,  G06F1/3237 ,  G06F1/3253 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D50/20

Abstract: A method and apparatus for dynamic clock and power gating and decentralized wakeups is disclosed. In one embodiment, an integrated circuit (IC) includes power-manageable functional units and a power management unit. Each of the power manageable functional units is configured to convey a request to enter a low power state to the power management unit The power management unit may respond by causing a requesting functional unit to enter the low power state. Should another functional unit initiate a request to communicate with a functional unit currently in the low power state, it may send a request to that functional unit. The receiving functional unit may respond to the request by exiting the low power state and resuming operation in the active state.

Abstract translation: 公开了一种用于动态时钟和电源门控和分散式唤醒的方法和装置。 在一个实施例中，集成电路（IC）包括功率可管理的功能单元和电源管理单元。 每个功率可管理功能单元被配置为向电力管理单元传送进入低功率状态的请求。电源管理单元可以通过使请求功能单元进入低功率状态来进行响应。 如果另一个功能单元发起与当前处于低功率状态的功能单元通信的请求，则它可以向该功能单元发送请求。 接收功能单元可以通过退出低功率状态并在活动状态下恢复运行来响应该请求。

公开(公告)号：WO2012071197A1

公开(公告)日：2012-05-31

申请号：PCT/US2011/060518

申请日：2011-11-14

Applicant: APPLE INC. ,  MACHNICKI, Erik P. ,  CHEN, Hao ,  MANSINGH, Sanjay

Inventor： MACHNICKI, Erik P. ,  CHEN, Hao ,  MANSINGH, Sanjay

IPC: H03L7/06

CPC classification number: H03L7/07 ,  H03L7/0814

Abstract: An efficient delay locked loop (DLL) training protocol during a frequency change includes an integrated circuit with a memory physical layer (PHY) unit that includes a master DLL and a slave DLL. The master DLL may delay a first reference clock by an amount, and provide a reference delay value corresponding to the delay amount. The slave DLL may delay a second reference clock by a second amount based upon a received configuration delay value. An interface unit may generate the configuration delay value based upon the reference delay value. A power management unit may provide an indication that the frequency of the second reference clock is changing. In response to receiving the indication, the interface unit may generate a new configuration delay value that corresponds to the new frequency using a predetermined scaling value and provide the new configuration delay value to the memory PHY unit.

Abstract translation: 在频率变化期间，有效的延迟锁定环（DLL）训练协议包括具有包含主DLL和从属DLL的存储器物理层（PHY）单元的集成电路。 主DLL可以将第一参考时钟延迟一定量，并提供对应于延迟量的参考延迟值。 从属DLL可以基于接收的配置延迟值将第二参考时钟延迟第二量。 接口单元可以基于参考延迟值生成配置延迟值。 功率管理单元可以提供第二参考时钟的频率正在改变的指示。 响应于接收到指示，接口单元可以使用预定的缩放值来生成对应于新频率的新的配置延迟值，并向存储器PHY单元提供新的配置延迟值。

公开(公告)号：EP3146408A1

公开(公告)日：2017-03-29

申请号：EP15716364.3

申请日：2015-04-01

Applicant: Apple Inc.

Inventor： TRIPATHI, Brijesh ,  KEIL, Shane J. ,  GULATI, Manu ,  CHO, Jung Wook ,  MACHNICKI, Erik P. ,  HERBECK, Gilbert H. ,  MILLET, Timothy J. ,  DE CESARE, Joshua P. ,  DALAL, Anand

IPC: G06F1/32

CPC classification number: G01D9/00 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/1689 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract translation: 在一个实施例中，芯片上的系统（SOC）包括当SOC的其余部分断电时保持供电的组件。 该组件可以包括用于从各种设备传感器捕获数据的传感器捕获单元，并且可以过滤所捕获的传感器数据。 响应于过滤，组件可以唤醒SOC的剩余部分以允许处理。 组件可以存储可编程配置数据，与SOC最近断电时的状态相匹配，用于SOC的其他组件，以便在唤醒后重新编程它们。 在一些实施例中，组件可以被配置为唤醒SOC内的存储器控​​制器和到存储器控制器的路径，以便将数据写入存储器。 SOC的其余部分可能仍然断电。

公开(公告)号：WO2017099861A1

公开(公告)日：2017-06-15

申请号：PCT/US2016/051967

申请日：2016-09-15

Applicant: APPLE INC.

Inventor： YU, Shu-Yi ,  MACHNICKI, Erik P. ,  HERBECK, Gilbert H. ,  KATTEL, Kiran B. ,  GULATI, Manu

IPC: G06F1/12 ,  G06F1/14

CPC classification number: G06F1/12 ,  G06F1/14

Abstract: In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.

Abstract translation: 在一个实施例中，诸如SOC（或者甚至是分立芯片系统）的集成电路在各个位置包括一个或多个本地时基。 时基可以基于在使用期间可能经历变化的高频本地时钟而增加。 周期性地，基于变化较小的较低频率的时钟，可以使用硬件电路将本地时基同步到正确的时间。 特别地，如果在同步之前本地时基达到正确值，则可以将用于下一同步的正确时基值传送给每个本地时基，并且可以将用于本地时基的控制电路配置为使本地时基饱和为正确的值 发生。 类似地，如果发生同步并且本地时基尚未达到正确值，则可以将控制电路配置为加载正确的时基值。

公开(公告)号：WO2012078334A1

公开(公告)日：2012-06-14

申请号：PCT/US2011/061197

申请日：2011-11-17

Applicant: APPLE INC. ,  DE CESARE, Josh P. ,  WADHAWAN, Ruchi ,  MACHNICKI, Erik P. ,  HAYTER, Mark D.

Inventor： DE CESARE, Josh P. ,  WADHAWAN, Ruchi ,  MACHNICKI, Erik P. ,  HAYTER, Mark D.

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F2213/2424 ,  Y02D10/14

Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.

Abstract translation: 在一个实施例中，中断控制器可以实现用于在多个处理器之间分配中断的中断分配方案。 该方案可以考虑在确定哪个处理器应该接收给定中断时的各种处理器状态。 例如，处理器状态可以包括处理器是否处于休眠状态，中断是否被使能，处理器是否响应先前的中断等。中断控制器可以实现超时机制以检测到 中断被延迟（例如，在提供给处理器之后）。 中断可能会在超时到期时重新评估，并可能提供给另一个处理器。 中断控制器可以被配置为自动并原子地屏蔽中断，以响应于将中断的中断向量传递给响应处理器。

公开(公告)号：WO2012050773A1

公开(公告)日：2012-04-19

申请号：PCT/US2011/052599

申请日：2011-09-21

Applicant: APPLE INC. ,  MILLET, Timothy J. ,  MACHNICKI, Erik P. ,  BALKAN, Deniz ,  GUPTA, Vijay

Inventor： MILLET, Timothy J. ,  MACHNICKI, Erik P. ,  BALKAN, Deniz ,  GUPTA, Vijay

IPC: G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/3275 ,  G06F1/3287 ,  G06F12/0802 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a control circuit is configured to transmit operations to a circuit block that is being powered up after being powered down, to reinitialize the circuit block for operation. The operations may be stored in a memory (e.g. a set of registers) to which the control circuit is coupled. In an embodiment, the control circuit may also be configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. Accordingly, the circuit block may be powered up or powered down even during times that the processors in the system are powered down (and thus software is not executable at the time), without waking the processors for the power up/power down event. In an embodiment, the circuit block may be a cache coupled to the one or more processors.

Abstract translation: 在一个实施例中，控制电路被配置为向断电后正在上电的电路块传送操作，以重新初始化电路块以进行操作。 操作可以存储在控制电路耦合到的存储器（例如一组寄存器）中。 在一个实施例中，控制电路还可以被配置为在电路块断电之前将其他操作从存储器传送到电路块。 因此，即使在系统中的处理器断电（并且因此软件不可执行的时候），即使在唤醒处理器以进行上电/断电事件的时间内，电路块也可以上电或掉电。 在一个实施例中，电路块可以是耦合到一个或多个处理器的高速缓存器。

公开(公告)号：WO2016160229A1

公开(公告)日：2016-10-06

申请号：PCT/US2016/020197

申请日：2016-03-01

Applicant: APPLE INC.

Inventor： TRIPATHI, Brijesh ,  SMITH, Eric G. ,  MACHNICKI, Erik P. ,  CHO, Jung Wook ,  ALASHMOUNY, Khaled M. ,  KATTEL, Kiran B. ,  BETTADA, Vijay M. ,  YANG, Bo ,  WEI, Wenlong

IPC: G01R19/165 ,  G01R19/10 ,  G01R31/28 ,  G01R23/165

CPC classification number: G05F3/02 ,  G06F1/324 ,  G06F1/3296

Abstract: An under voltage detection circuit and method of operating an IC including the same is disclosed. In one embodiment, an IC includes an under voltage protection circuit having first and second comparators configured to compare a supply voltage to first and second voltage thresholds, respectively, with the second voltage threshold being greater than the first. A logic circuit is coupled to receive signals from the first and second comparators. During operation in a high performance state by a corresponding functional circuit, the logic circuit is configured to cause assertion of a throttling signal responsive to an indication that the supply voltage has fallen below the first threshold. A clock signal provided to the functional circuit may be throttled responsive to the indication. If the supply voltage subsequently rises to a level above the second threshold, the throttling signal may be de-asserted.

Abstract translation: 公开了一种欠压检测电路及其运算方法。 在一个实施例中，IC包括欠压保护电路，其具有第一和第二比较器，其被配置为分别将电源电压与第一和第二电压阈值进行比较，其中第二电压阈值大于第一电压阈值。 逻辑电路被耦合以从第一和第二比较器接收信号。 在通过相应的功能电路在高性能状态下操作期间，逻辑电路被配置为响应于电源电压已经低于第一阈值的指示而导致节流信号的断言。 提供给功能电路的时钟信号可以响应于指示而被节流。 如果电源电压随后上升到高于第二阈值的水平，则节流信号可以被取消断言。

公开(公告)号：WO2016053490A1

公开(公告)日：2016-04-07

申请号：PCT/US2015/045585

申请日：2015-08-17

Applicant: APPLE INC.

Inventor： DE LA CROPTE DE CHANTERAC, Cyril ,  GULATI, Manu ,  MACHNICKI, Erik P. ,  COX, Keith ,  MILLET, Timothy J.

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172

Abstract: Embodiments of a method that allow the adjustment of performance settings of a computing system are disclosed. One or more functional units may include multiple monitor circuits, each of which may be configured to monitor a given operational parameter of a corresponding functional unit. Upon detection of an event related to a monitored operational parameter, a monitor circuit may generate an interrupt. In response to the interrupt a processor may adjust one or more performance settings of the computing system.

Abstract translation: 公开了允许调整计算系统的性能设置的方法的实施例。 一个或多个功能单元可以包括多个监视器电路，每个监视器电路可以被配置为监视对应功能单元的给定操作参数。 在检测到与所监视的操作参数有关的事件时，监视器电路可产生中断。 响应于中断，处理器可以调整计算系统的一个或多个性能设置。

公开(公告)号：WO2014113466A1

公开(公告)日：2014-07-24

申请号：PCT/US2014/011673

申请日：2014-01-15

Applicant: APPLE INC.

Inventor： KEIL, Shane J. ,  MACHNICKI, Erik P. ,  DE CESARE, Josh P.

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203

Abstract: Techniques are disclosed relating to power management within an integrated circuits. In one embodiment an apparatus is disclosed that includes a circuit and a power management unit. The power management unit is configured to provide, based on a programmable setting, an indication of whether an attempted communication to the circuit is permitted to cause the circuit to exit from a power-managed state. In some embodiments, the apparatus includes a fabric configured to transmit the attempted communication to the circuit from a device. In such an embodiment, the circuit is configured to exit the power-managed state in response to receiving the attempted communication. The fabric is configured to determine whether to transmit the attempted communication based on the indication provided by the power management unit.

Abstract translation: 公开了与集成电路内的电力管理有关的技术。 在一个实施例中，公开了一种包括电路和电源管理单元的装置。 功率管理单元被配置为基于可编程设置来提供是否允许对电路的尝试通信是使电路退出功率管理状态的指示。 在一些实施例中，该装置包括被配置成从设备将尝试的通信传送到电路的结构。 在这样的实施例中，电路被配置为响应于接收到尝试的通信而退出功率管理状态。 结构被配置为基于由电力管理单元提供的指示来确定是否发送尝试的通信。