公开(公告)号：US10932371B2

公开(公告)日：2021-02-23

申请号：US14933315

申请日：2015-11-05

Applicant: CORNING INCORPORATED

Inventor： Robert Alan Bellman ,  John Tyler Keech ,  Ekaterina Aleksandrovna Kuksenkova ,  Scott Christopher Pollard

IPC: H05K3/00 ,  H05K3/42 ,  C25D7/12 ,  H01L21/48 ,  C25D5/02 ,  H01L21/768 ,  H01L23/15 ,  C25D1/04 ,  H01L23/498

Abstract: Disclosed herein is a bottom-up electrolytic via plating method wherein a first carrier substrate and a second substrate having at least one through-via are temporarily bonded together. The method includes applying a seed layer on a surface of the first substrate, forming a surface modification layer on the seed layer or the second substrate, bonding the second substrate to the first substrate with the surface modification layer to create an assembly wherein the seed layer and the surface modification layer are disposed between the first and second substrates, applying conductive material to the through-via, removing the second substrate having the through-via containing conductive material from the assembly.

公开(公告)号：US20200165160A1

公开(公告)日：2020-05-28

申请号：US16776663

申请日：2020-01-30

Applicant: CORNING INCORPORATED

Inventor： Mandakini Kanungo ,  Prantik Mazumder ,  Chukwudi Azubuike Okoro ,  Ah-Young Park ,  Scott Christopher Pollard ,  Rajesh Vaddi

IPC: C03C17/06 ,  C23C18/38 ,  H05K1/03 ,  H01L23/498 ,  H01L23/15 ,  C23C14/18 ,  H01L21/768 ,  H05K1/11 ,  C23C28/02 ,  H05K1/02 ,  C25D7/12

Abstract: According to various embodiments described herein, an article comprises a glass or glass-ceramic substrate having a first major surface and a second major surface opposite the first major surface, and a via extending through the substrate from the first major surface to the second major surface over an axial length in an axial direction. The article further comprises a helium hermetic adhesion layer disposed on the interior surface; and a metal connector disposed within the via, wherein the metal connector is adhered to the helium hermetic adhesion layer. The metal connector coats the interior surface of the via along the axial length of the via to define a first cavity from the first major surface to a first cavity length, the metal connector comprising a coating thickness of less than 12 μm at the first major surface. Additionally, the metal connector coats the interior surface of the via along the axial length of the via to define a second cavity from the second major surface to a second cavity length, the metal connector comprising a coating thickness of less than 12 μm at the second major surface and fully fills the via between the first cavity and the second cavity.

公开(公告)号：US20180249579A1

公开(公告)日：2018-08-30

申请号：US15754144

申请日：2016-08-19

Applicant: Corning Incorporated

Inventor： Sean Matthew Garner ,  Samuel Odei Owusu ,  Garrett Andrew Piech ,  Scott Christopher Pollard

IPC: H05K3/00 ,  H05K1/03 ,  H05K1/02 ,  H05K3/40 ,  H05K1/11 ,  C03C23/00 ,  C03C15/00 ,  C03C17/00

CPC classification number: H05K3/0029 ,  C03B33/0222 ,  C03C15/00 ,  C03C17/002 ,  C03C17/008 ,  C03C23/0025 ,  C03C23/007 ,  C03C2217/445 ,  C03C2217/70 ,  H01L21/4807 ,  H01L23/15 ,  H05K1/024 ,  H05K1/028 ,  H05K1/0306 ,  H05K1/036 ,  H05K1/115 ,  H05K3/002 ,  H05K3/107 ,  H05K3/388 ,  H05K3/4038 ,  H05K3/4629 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2203/0143 ,  H05K2203/0743 ,  H05K2203/075 ,  H05K2203/0776 ,  H05K2203/0789 ,  H05K2203/107 ,  H05K2203/1194 ,  H05K2203/1545 ,  Y02P40/57

Abstract: Methods of continuous fabrication of features in flexible substrates are disclosed. In one embodiment, a method of fabricating features in a substrate web includes providing the substrate web arranged in a first spool on a first spool assembly, advancing the substrate web from the first spool and through a laser processing assembly comprising a laser, and creating a plurality of defects within the substrate web using the laser. The method further includes advancing the substrate web through an etching assembly and etching the substrate web at the etching assembly to remove glass material at the plurality of defects, thereby forming a plurality of features in the substrate web. The method further includes rolling the substrate web into a final spool.

公开(公告)号：US09472479B2

公开(公告)日：2016-10-18

申请号：US14608537

申请日：2015-01-29

Applicant: CORNING INCORPORATED

Inventor： Satish Chandra Chaparala ,  Scott Christopher Pollard

IPC: H01L21/00 ,  H01L23/15 ,  H01L23/00 ,  H05K1/02 ,  H05K1/18 ,  H01L23/498

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H05K1/0201 ,  H05K1/181 ,  H05K2201/068 ,  H01L2924/00

Abstract: Methods and apparatus are provide for an interposer for interconnecting one or more semiconductor chips with an organic substrate in a semiconductor package, the interposer including: a first glass substrate having first and second opposing major surfaces, the first glass substrate having a first coefficient of thermal expansion (CTE1); a second glass substrate having first and second opposing major surfaces, the second glass substrate having a second coefficient of thermal expansion (CTE2); and an interface disposed between the first and second glass substrates and joining the second major surface of the first glass substrate to the first major surface of the second glass substrate, where CTE1 is less than CTE2, the first major surface of the first glass substrate operates to engage the one or more semiconductor chips, and the second major surface of the second glass substrate operates to engage the organic substrate.

Abstract translation: 提供了用于将一个或多个半导体芯片与半导体封装中的有机衬底互连的插入件的方法和装置，所述插入器包括：具有第一和第二相对主表面的第一玻璃衬底，所述第一玻璃衬底具有第一热导率 扩展（CTE1）; 具有第一和第二相对主表面的第二玻璃基板，所述第二玻璃基板具有第二热膨胀系数（CTE2）; 以及设置在第一和第二玻璃基板之间并且将第一玻璃基板的第二主表面接合到第二玻璃基板的第一主表面的接口，其中CTE1小于CTE2，第一玻璃基板的第一主表面操作 以接合一个或多个半导体芯片，并且第二玻璃基板的第二主表面操作以接合有机基板。