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    21.
    发明专利
    未知

    公开(公告)号：ITTO960326A1

    公开(公告)日：1997-10-24

    申请号：ITTO960326

    申请日：1996-04-24

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BOSTICA BRUNO ,  BURZIO MARCO ,  PELLEGRINO PAOLO ,  PESANDO LUCA

    IPC: H01L27/092 ,  H01L21/8238 ,  H01S5/042 ,  H01S5/068 ,  H01S5/40 ,  H04B10/04 ,  H04B10/06 ,  H04B10/142 ,  H04B10/152

    Abstract: The circuit comprises bias and modulation current generators (T1...T6) for both p-type and n-type optical sources, and a pair of sources of control voltages (B, M) for the bias and modulation current generators, which obtain pairs of control voltages from an adjustable driving current. An external signal allows selecting, by means of a control logic (LC) and CMOS gates (P1...P6), the generators required by the source (LA). The circuit is made by using three pads of an integrated circuit, one for each control voltage source (B, M) and the third (D) comprising the current generators (T1...T6), the CMOS gates (P1...P6) and the control logic (LC).

    Serialising-Parallelising Circuit for High Speed Digital Signals
    22.
    发明专利
    Serialising-Parallelising Circuit for High Speed Digital Signals 未知

    公开(公告)号：CA2190069A1

    公开(公告)日：1997-05-14

    申请号：CA2190069

    申请日：1996-11-12

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： PELLEGRINO PAOLO ,  BURZIO MARCO

    IPC: H04L7/08 ,  H03M9/00 ,  H04J3/04 ,  H04L12/56 ,  H04Q3/00 ,  H04Q11/04 ,  H04L9/00

    Abstract: The serializing-parallelizing circuit comprises, on a single integrated circuit chip (IC), a transmitter (TX) which performs the parallel-to-series conversion of the data stream, the insertion into the serial stream, with a pre-set periodicity, of a synchronism word, and the line coding of the serial stream, and a receiver (RX) in which clock signals synchronous with the data stream are extracted from a serial stream of coded data and in which the data are decoded and the decoded signals undergo series-to-parallel conversion. The transmitter (TX) and the receiver (RX) can be configured to operate with 4 or 8-bit parallelism.

    Circuit for Clock Signal Extraction from a High Speed Data Stream
    28.
    发明专利
    Circuit for Clock Signal Extraction from a High Speed Data Stream 未知

    公开(公告)号：CA2171690A1

    公开(公告)日：1996-09-15

    申请号：CA2171690

    申请日：1996-03-13

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BURZIO MARCO

    IPC: H03K19/0175 ,  H03D13/00 ,  H03L7/085 ,  H03L7/087 ,  H03L7/089 ,  H03L7/113 ,  H03L7/14 ,  H04L7/033

    Abstract: The circuit for clock signal extraction from a high speed data stream allows a rapid attainment of the identity between the frequencies of the locally generated clock signal and of the data signal, even when such frequencies are very different. The circuit can easily be inserted into a more complex CMOS digital integrated circuit, it has low power dissipation and is capable of operating at bit rates exceeding 300 Mbit/s. The circuit comprises a main phase locked loop, which controls a voltage controlled oscillator by continually controlling its phase, and a secondary loop, which allows the main loop to become locked, by causing the voltage controlled oscillator to oscillate at a frequency close to the operating frequency.

    29.
    发明专利
    未知

    公开(公告)号：ITTO950190A1

    公开(公告)日：1996-09-14

    申请号：ITTO950190

    申请日：1995-03-14

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BURZIO MARCO

    IPC: H03K19/0175 ,  H03D13/00 ,  H03L7/085 ,  H03L7/087 ,  H03L7/089 ,  H03L7/113 ,  H03L7/14 ,  H04L7/033

    Abstract: The circuit for clock signal extraction from a high speed data stream allows a rapid attainment of the identity between the frequencies of the locally generated clock signal and of the data signal, even when such frequencies are very different. The circuit can easily be inserted into a more complex CMOS digital integrated circuit, it has low power dissipation and is capable of operating at bit rates exceeding 300 Mbit/s. The circuit comprises a main phase locked loop, which controls a voltage controlled oscillator by continually controlling its phase, and a secondary loop, which allows the main loop to become locked, by causing the voltage controlled oscillator to oscillate at a frequency close to the operating frequency.

    INTEGRATED CIRCUIT PHASE-LOCKED LOOP CHARGE PUMP
    30.
    发明专利
    INTEGRATED CIRCUIT PHASE-LOCKED LOOP CHARGE PUMP 未知

    公开(公告)号：CA2312349C

    公开(公告)日：2003-08-19

    申请号：CA2312349

    申请日：2000-06-21

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BURZIO MARCO ,  BALISTRERI EMANUELE

    IPC: H03L7/093 ,  H03L7/089 ,  H03L7/085

    Abstract: A charge pump (2) is supplied to reset in rated conditions the error signal of a phase-locked loop of the type whereby a phase detector (1) periodically supplies this pump (2) with a first and second impulse having emission instants dependent on the phase ratio between phase-locked loop input signals and are allocated to control circuit output increase or decrease respectively by means of ring filter (3a, 3b). The pump features loops (21, 22, 23, 24, 28) to transform the first and second impulse into a first and second voltage signal of longer duration than maximum impulse duration and featuring values the difference of which depends on the phase ratio between the loop input signals and to generate a signal in a current representative of such difference.

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