公开(公告)号：JPS57211845A

公开(公告)日：1982-12-25

申请号：JP9662881

申请日：1981-06-24

Applicant: FUJITSU LTD

Inventor： KITANO YOSHIHIRO ,  MITA TERUYOSHI

IPC: H04B10/00 ,  H04B10/07 ,  H04B10/27 ,  H04B10/275 ,  H04B10/29 ,  H04B10/524 ,  H04B10/80 ,  H04L12/42

Abstract: PURPOSE:To apply electric power to a station node at the input of light to an optical transmission line by providing a titled system with a highway monitoring device and the station node both of which use the looplike optical transmission line in common. CONSTITUTION:When an optical signal is transmitted from a highway monitoring device to an optical transmission line l and applied to an optical repeater 1 of a station node, a photodiode 6 is connected and current flows from a cell in a controlling part 4 to a relay winding 3, connecting a relay contact rl. Subsequently, a main switch driving circuit in a controlling part 4 is actuated and a main switch S is connected, so that commercial electric power AC 100V is applied to an electric power source part 5 and required electric power is supplied from the power source part 5 to a logical device 2. In addition, the power source part 5 charges the cell in the controlling part 4.

公开(公告)号：JPS5765038A

公开(公告)日：1982-04-20

申请号：JP14161180

申请日：1980-10-09

Applicant: Fujitsu Ltd

Inventor： IIJIMA KOUJI ,  MITA TERUYOSHI

IPC: H04L1/00 ,  H04L12/43

CPC classification number: H04L12/43

Abstract: PURPOSE:To monitor circulating data simply with good transmission efficiency, by concentratingly monitoring the data at the monitor station and performing the abolition of the circulating data completely, through the provision of two types of 2-bit flag area in the data format. CONSTITUTION:A monitor station SV monitoring data and a plurality of node stations ND1-ND4 are connected in loop with a transmission line to constitute the loop network. In the data format of the time slot used for this network, a control area 1, opposing party address area 2, data area 3 and check bit area 4 are provided, and the area 1 is provided with a monitor station passing flag bit SV flag and a usage display flag bit B/I flag. When data are transmitted at stations ND1- ND4, the B/I flag is set, and the SV flag is set when the time slot passes through the monitor station SV, and when both the SV and B/I flag are detected at the monitor station SV, the data of the time slot is abolished.

Abstract translation: 目的：通过集中监控监控站的数据，完全废除循环数据，通过提供数据格式的两种类型的2位标志区域来监控循环数据。 构成：监视站SV监视数据和多个节点站ND1-ND4与传输线环路连接，构成环路网络。 在用于该网络的时隙的数据格式中，提供控制区域1，对方地址区域2，数据区域3和校验位区域4，并且区域1设置有通过标志位SV标志的监视站 和使用显示标志位B / I标志。 当数据在站点ND1- ND4发送时，设置B / I标志，并且当时隙通过监视站SV时设置SV标志，并且当监视器检测到SV和B / I标志时 站SV，时隙的数据被取消。

公开(公告)号：JPS55134461A

公开(公告)日：1980-10-20

申请号：JP4179779

申请日：1979-04-06

Applicant: FUJITSU LTD

Inventor： SATOU MASAO ,  MITA TERUYOSHI ,  HOSHI FUMIO

IPC: G06F12/16 ,  G06F12/06 ,  G06F13/00 ,  G11C7/00

Abstract: PURPOSE:To make it possible to access an address designated by address information correctly, by constituting a system so that the memory part to be accessed may be determined on a basis of a mounting signal, a mounting position signal and address information. CONSTITUTION:It is assumed that a high-speed memory array board and a low- speed memory array board are mounted in high-speed memory mounting position 2-1 and mounting position 2-4 of low-speed memory mounting area 3 respectively. In case that the access address is included in addresses 0-128K, signal MCYA is turned on because signal MSUA is turned on, and timing control circuit 5 generates a signal required for access of the high-speed memory part to access the high-speed memory part. In case that the access address is included in addresses 128K-512K, the output of gate 6 becomes logical 1, and signal MSUB and signal YB are turned on. Circuit 5 generates a signal required for access of the low-speed memory part to access the low-speed memory part.

公开(公告)号：JPS55134455A

公开(公告)日：1980-10-20

申请号：JP4072179

申请日：1979-04-04

Applicant: FUJITSU LTD

Inventor： HOSHI FUMIO ,  MITA TERUYOSHI ,  SATOU MASAO

IPC: G06F11/10

Abstract: PURPOSE:To give a very simple constitution to a circuit by constituting the circuit so that a new parity bit can be obtained by the parity bit of a data processing circuit and data of a part of it. CONSTITUTION:Data group A is output from data processing circuit 1. Data a2 of this data group A is processed into data a3 by data processing circuit 3. Accompanied with this processing, new parity bit p2 is formed according to data a2 and parity bit p1 by parity forming circuit 7. In circuit 7, data a2 is transferred to exclusive OR circuit E1 for every bit, and bit P1 is transferred to exclusive OR circuit E2, and the output of circuit E1 is transferred to the other input of circuit E2. Consequently, since data a2 is 10 and bit P1 is 1 now, logic 1 is output from circuit E1, and logic 0 is output from circuit E2, and bit P2 becomes logic 0. Thus, parity bit P2 can be obtained with a very simple circuit.

公开(公告)号：JPS54102934A

公开(公告)日：1979-08-13

申请号：JP950178

申请日：1978-01-31

Applicant: FUJITSU LTD

Inventor： SUZUKI YOUICHI ,  KUGIMIYA SETSUO ,  HANADA AKIO ,  MITA TERUYOSHI ,  NAKAMURA HIROSHI

IPC: G06F13/14 ,  G06F3/00 ,  G06F15/16 ,  G06F15/177

Abstract: PURPOSE:To secure the comminucation for more than a fixed time between one unit of CPU and IO by providing the means to select the remote CPU and to memorize the start request to the IO in the communication control system in which the input/output device IO connected with plural CPU's is shared. CONSTITUTION:The IO turns on one bit in selection register 4 via the program and then accepts the start request from the corresponding CPU. In case the start requests are given from other CPU's, the busy signal is sent back from FF1 and corresponding one bit in start request memory register 3 is turned on since the selection bit corresponding to the CPU is off. AFter end of the communication, the CPU with which the bit of register 3 is turned on is selected. Thus, the communication end information is sent to the CPU, and at the same time one bit in register 3 is turned off. The selection bit is informed to the program after communication and turned off simultaneously. Thus, the priority-selected CPU and IO are displayed to be in use even though the communication is carried out between them, ensuring the communication of more then a fixed time.

公开(公告)号：JPS5492148A

公开(公告)日：1979-07-21

申请号：JP16045877

申请日：1977-12-29

Applicant: FUJITSU LTD

Inventor： SUZUKI YOUICHI ,  HANADA AKIO ,  MITA TERUYOSHI ,  HOSHI FUMIO ,  SATOU MASAO

IPC: G06F7/00 ,  G06F9/46 ,  G06F13/00

Abstract: PURPOSE:To make it possible to use conventionally-designed programs and newly- designed programs after extension, which are mixed, by providing a program discriminating method and control operation changing method. CONSTITUTION:Bits received by line set 5-i are built up 4 into one character and an interruption is made to central controller 1. Next, controller 1 discriminates what line set the data come from to inform circuit connection device 4 of the address of memory unit 2 where data will be stored and then indicates channel adaptor 3 that when a fixed number of characters are built up, data are transmitted to the host computer. For example, when a data communication system is extended assuming that line sets before extension are 5-0 to 5-31 and extended ones are 5-32 and 5-33, interruptions to line sets 5-0 to 5-31 are processed by conventional programs before the extension, namely, BC-mode exclusive-use programs and interruptions to extended ones are processed by newly-designed, namely, EC-mode exclusive-use programs.

公开(公告)号：JPS62174853A

公开(公告)日：1987-07-31

申请号：JP1631286

申请日：1986-01-28

Applicant: FUJITSU LTD

Inventor： MITA TERUYOSHI

IPC: H04L29/10 ,  G06F13/00 ,  H04L13/00

Abstract: PURPOSE:To shorten an idle time on a circuit by overlapping the communication time between a communication processing mechanism and a circuit control mechanism on a data sending time from a local data buffer to a circuit. CONSTITUTION:The said device consists of a communication processing mechanism 1 and a circuit control mechanism 2, and the communication processing mechanism 1 has the first command control mechanism 10, an interrupting control mechanism 11, a main memory device 14 and a cycle steal mechanism 13. The circuit control mechanism 2 has the second instruction control mechanism 21, a control memory device 25, a circuit connecting mechanism 24 and a cycle steel mechanism 23. The circuit controlling mechanism 2 operates the cycle steal mechanism, transfers a transmitting data from a transmitting data buffer to a local data buffer, and sends a data being stored in the local data buffer to the circuit. It further informs the communication processing mechanism of the completion of transmission by the completion of data transfer from the transmission data buffer to the local data buffer.

公开(公告)号：JPS622745B2

公开(公告)日：1987-01-21

申请号：JP15309380

申请日：1980-10-31

Applicant: FUJITSU LTD

Inventor： SATO KEIJI ,  NAKAMURA YOSHIHIRO ,  MITA TERUYOSHI ,  KITANO YOSHIHIRO ,  YATSUHOSHI AKIMASA

IPC: H04L12/42

公开(公告)号：JPS61240739A

公开(公告)日：1986-10-27

申请号：JP8187085

申请日：1985-04-17

Applicant: FUJITSU LTD

Inventor： NAKAHARA YASUHIRO ,  MITA TERUYOSHI ,  KITANO YOSHIHIRO ,  NEGISHI HITOSHI ,  NAKAMURA OSAMU ,  INOUE YUKINORI

Abstract: PURPOSE:To shorten the check time of a list sequence, and to improve the real time property of a system by providing a function for detecting quickly a list sequence error of a station node for forming an annular data transmission line. CONSTITUTION:In a data highway system which has been constituted of a network monitoring device NSP 1, a highway monitoring device SV 2, and station nodes SN 1-5, etc., a function for detecting quickly a list sequence error of the SNs 1-5 is provided. That is to say, a control part FLEO 44 for generating and releasing a spurious transmission line fault, an FLE 148, etc. are provided, and a start for generating the spurious transmission line fault to the SV 2 or the SNs 1-5 is executed. As a result, the spurious transmission line fault of a LINE '0' system is propagated to SN3, SN2, SN4 and SN5 through SN1 of the '0' system, and when the fault is detected by the SN2, it is informed to the NSP 1. Also, even in case of a LINE '1' system, the processing is executed in the same way. By such a processing, a list sequence can be checked quickly, the releasing work time is shortened, and the real time property of the system can be improved.

公开(公告)号：JPS61150544A

公开(公告)日：1986-07-09

申请号：JP27601484

申请日：1984-12-25

Applicant: FUJITSU LTD

Inventor： NAKAMURA OSAMU ,  MITA TERUYOSHI ,  KITANO YOSHIHIRO ,  NAKAHARA YASUHIRO ,  NEGISHI HITOSHI

Abstract: PURPOSE:To improve the use efficiency of a time slot by executing data transmission to the other terminal from one terminal by loading data on an assigned time slot, and executing data transmission to one terminal from the other terminal by using an in-node data bus means, in case when point-to-point communication between each of a pair of terminals of plural terminals which have been connected to the same node. CONSTITUTION:In continuous time slots TSi, TSi+1, TSi and TSi+1 are assigned to a circuit corresponding part A and a circuit corresponding part B, respectively. When TSi comes to a buffer 9, the circuit corresponding part A raises a processing request status, a control part 13 allows a selector 14 to select an input 1 by a signal 1, and data (a transmitting data from the terminal B) of TSi in the buffer 9 is read into the circuit corresponding part A. When TSi+1 comes to the buffer 9, transmitting data from the circuit corresponding part A is read into the circuit corresponding part B, and also a signal 18 is controlled so that the contents of an input 2 are inputted to a P/S converter 11 by the next shift clock.