公开(公告)号：JPH01166144A

公开(公告)日：1989-06-30

申请号：JP32501287

申请日：1987-12-22

Applicant: FUJITSU LTD

Inventor： NOJIMA SATOSHI ,  TSUTSUI HIDEKAZU ,  SAKAKAWA KAZUO ,  SHIBAYAMA TAKENOBU

IPC: G06F11/28

Abstract: PURPOSE:To realize a firmware program debug function with little hardware by using an ECC memory as a trace memory and providing a counter as a trace code generating means. CONSTITUTION:First, the address of an instruction step to start the debug of the firmware program is designated and a trace code is written into an ECC memory 2. At the time of executing the above-mentioned program, the trace code is read out. A trace control circuit 3 resets a counter and makes it start a count action when it detects the trace code and makes it stop it when it reaches a prescribed value. The counter 6 counts +1 and generates the trace code of a sequence number to change in a rising sequence each time a program memory 1 is accessed. The trace code generated by the counter 6 is written into the address of the ECC memory 2 accessed at that time.

公开(公告)号：JPS6458038A

公开(公告)日：1989-03-06

申请号：JP21421187

申请日：1987-08-28

Applicant: FUJITSU LTD

Inventor： NOJIMA SATOSHI ,  SAKAKAWA KAZUO

IPC: G06F13/12

Abstract: PURPOSE:To eliminate deterioration of the throughput at the transfer by discriminating an interlock system when the time is constantly fixed between the input and output changing points of two tag answer circuits and then deciding a DSF (data streaming feature) system when said time is variable. CONSTITUTION:A 1st tag answer circuit 5 transmits an answer tag signal with no delay against the tag signal sent to a channel from an input/output device, etc. While a 2nd tag answer circuit 6 transmits an answer tag signal after a fixed delay. A control circuit 11 usually transmits the output of the circuit 5 then transmits the outputs of both circuits 5 and 6 alternately at the time of discriminating the transfer system. At the time of discriminating, a transfer system discriminating means 10 counts the time required between a state changing point of the answer tag signals transmitted from both circuits 5 and 6 and that of the answer tag signals supplied to those circuits 5 and 6. Then the means 10 discriminates as an interlock transfer system when said time count value is constantly fixed by the prescribed frequency, then discriminates as a DSF system when the time count value is not fixed.

公开(公告)号：JPS63229556A

公开(公告)日：1988-09-26

申请号：JP6240687

申请日：1987-03-19

Applicant: FUJITSU LTD

Inventor： SAKAKAWA KAZUO ,  FUKUDA HARUKI ,  NOJIMA SATOSHI

IPC: G06F13/10 ,  G06F13/12

Abstract: PURPOSE:To improve the throughput for transfer of data by giving access only to those nodes set under the control of a selected control unit after the control units are decided. CONSTITUTION:The selection signals received from a channel CH2 are transmitted simultaneously to control units CU4-1-4-6 which control nodes S6-1-6-3 via these nodes. A node C stores the answers informed from the units CU4-1-4-6. Based on the result of said storage, the information on the CH2 is transmitted only to the node S6-2, for example, containing the selected unit 4-3. Thus the 1:1 connection is secured between the channel CH and the selected control unit CU.

公开(公告)号：JPS6376645A

公开(公告)日：1988-04-06

申请号：JP22233686

申请日：1986-09-19

Applicant: FUJITSU LTD

Inventor： FUKUDA HARUKI ,  NOJIMA SATOSHI ,  TSUTSUI HIDEKAZU ,  KANOUCHI JUNICHI ,  TOMINAGA SUSUMU

Abstract: PURPOSE:To secure a communication line for a data packet group with highpriority although a one with low priority is abandoned in case packet switching network are duplicated by splitting data that a terminal equipment outputs into plural packet groups with priority according to their contents. CONSTITUTION:Terminal equipments 5A, 5B and 5C receive data packets with different degrees of priority. If the communication volume of 2B out of bypassed relay lines 2B and 2C exceeds a tolerance in case of a fault at a place 21 on a relay line 2A, among data packets that the terminal equipments 5A, 5B and 5C output, a communication line 41 for data packets with low priority that the terminal equipments. Aa and 5B output is abandoned in the relay line 2B, and a communication line 32 for data packets with high priority replaces. As for the relay line 2B between switchboards 1A and 1B, a communication line 42 for data packets with low priority is abandoned, and only the communication line 32 for data packets with high priority that equipments 5Ab and 5C output is maintained.

公开(公告)号：JPS6250008B2

公开(公告)日：1987-10-22

申请号：JP22452282

申请日：1982-12-21

Applicant: FUJITSU LTD

Inventor： AZUMA MITSUHIRO ,  TAKEYAMA AKIRA ,  NOJIMA SATOSHI ,  TAZAKI TAKASHI ,  MATSUDA MASAHIRO

IPC: H04L12/42 ,  H04B3/46 ,  H04L12/437

公开(公告)号：JPS62186632A

公开(公告)日：1987-08-15

申请号：JP2837586

申请日：1986-02-12

Applicant: FUJITSU LTD

Inventor： NOJIMA SATOSHI ,  TSUTSUI HIDEKAZU ,  TOMINAGA SUSUMU

IPC: H04Q3/52

Abstract: PURPOSE:To prevent packet abolition state due to occupied buffer by providing an auxiliary route forming a bypass route to a first-in first-out buffer. CONSTITUTION:Routes 601, 602, 701, 702, 801 absorbing the overflow of buffer are provided. That is, the memory quantity of the 3rd buffer 10 is selected in matching with an average traffic and as a normal route, routes toward the 1st buffer 6, 1st bus 8, 3rd bus 10, 2nd bus 9 and 2nd buffer are given. If the traffic increase momentarily, the route absorbing the overflow of buffer is formed in parallel with the 3rd buffer 10 used for the normal route. Thus, the occurrence of packet abolition state due to the overflow packet is prevented.

公开(公告)号：JPS59122042A

公开(公告)日：1984-07-14

申请号：JP22452182

申请日：1982-12-21

Applicant: Fujitsu Ltd

Inventor： TAZAKI TAKASHI ,  TAKEYAMA AKIRA ,  NOJIMA SATOSHI ,  AZUMA MITSUHIRO ,  MATSUDA MASAHIRO

IPC: H04L1/22 ,  H04B1/74 ,  H04L12/437

CPC classification number: H04L12/437

Abstract: PURPOSE:To prevent discontinuation occurring to frames at the switching of transmission lines and to suppress data errors by providing a data invalidation period in a frame consisting of plural bits, and detecting this invalidation period by a data invalidation period detecting means provided in a communication device. CONSTITUTION:A communication system consists of transmission lines 3 and 4 which are used by switching an in-use and a stand-by system and plural nodes 20 which switch the transmission lines 3 and 4 by a transmission line switch 70 through repeaters 50 and 60. The frame unit of data transmitted between nodes 20 of this communication system consists of a flag F, control part C, data D, detection parts FCS, and data invalidation period B. Invalidation period detecting means 51 and 61 which detect this invalidation period B are provided to the repeaters 50 and 60 respectively. Then, switch parts 76 and 77 are controlled by a common control part 80 in the invalidation period to prevent discontinuation which occurs to frames during the switching of the transmission lines 3 and 4, suppressing errors of data.

Abstract translation: 目的：为了防止在传输线路切换时发生帧停止，并且通过在由多个比特组成的帧中提供数据无效周期来抑制数据错误，并且通过设置在通信设备中的数据无效期检测装置来检测该无效期间 。 构成：通信系统由传输线路3和4组成，它们通过切换使用中和使用的备用系统以及多个节点20通过中继器50和60由传输线路开关70切换传输线路3和4 在该通信系统的节点20之间发送的数据的帧单位由标志F，控制部C，数据D，检测部FCS，数据无效期B构成。无效期检测装置51和61检测该无效期间B 分别提供给中继器50和60。 然后，在无效期间，通过公共控制部分80控制开关部分76和77，以防止在传输线路3和4的切换期间对帧发生的中断，从而抑制数据的错误。

公开(公告)号：JPS5925449A

公开(公告)日：1984-02-09

申请号：JP13459082

申请日：1982-07-31

Applicant: Fujitsu Ltd

Inventor： TAKEYAMA AKIRA ,  TAZAKI TAKASHI ,  NOJIMA SATOSHI ,  MITA TERUYOSHI

IPC: H04L7/02 ,  H04L7/00

CPC classification number: H04L7/00

Abstract: PURPOSE:To perform the effective switching for the clock signal source of a receiving station with a simple constitution, by executing a logical operation about the condition of a switch request signal and the condition under which the output of clock signal source is the same in phase to each other, and switching the results to prescribed values. CONSTITUTION:For a selecting/switching circuit in a deciding circuit, the left and right sides centering on a chain line show a common part CM and a part CH which can be increased for each channel. A frequency divider DV1 obtains a frequency FH of FO/(N-1) and a frequency FL of FO/(N+1) respectively, where FO and N show an input clock frequency of a receiving station and an integer respectively. A counter MOD delivers the least common multiple of (N-1).(N+ 1). A circuit LG performs an AND operation between a request signal CQR and the output E of a comparator CMP. Then an FF is reset by the next signal CRQ if an output Fout is equal to FH when the FF is set. Therefore, the output Fout is changed to FL.

Abstract translation: 目的：以简单的结构对接收站的时钟信号源进行有效切换，通过执行关于切换请求信号的条件的逻辑运算以及时钟信号源的输出在相位上相同的条件 并将结果切换到规定的值。 构成：对于决定电路中的选择/切换电路，以链线为中心的左右两侧显示公共部分CM和可以为每个通道增加的部分CH。 分频器DV1分别获得FO /（N-1）的频率FH和FO /（N + 1）的频率FL，其中FO和N分别表示接收站的输入时钟频率和整数。 计数器MOD提供（N-1）（N + 1）的最小公倍数。 电路LG在请求信号CQR和比较器CMP的输出E之间执行“与”运算。 然后，当FF置位时，如果输出Fout等于FH，则FF由下一个信号CRQ复位。 因此，输出Fout变为FL。

公开(公告)号：JPS58116835A

公开(公告)日：1983-07-12

申请号：JP21362181

申请日：1981-12-29

Applicant: FUJITSU LTD

Inventor： TAZAKI TAKASHI ,  TAKEYAMA AKIRA ,  ARITAKA TOKUHIRO ,  NOJIMA SATOSHI

IPC: H04L12/40

Abstract: PURPOSE:To prevent the occurrence of a data error during node extension by inserting an extension transmission line into a main transmission line after obtaining the synchronism of data on the main transmission line with that on the extension transmission line. CONSTITUTION:An existent node 100 is equipped with a T branch circuit 10, synchronizing elastic buffer 11, and transmission line 12 and is connected to a transmission line. When an extension node 20 is added to it nearly, a signal branched from the circuit 10 is transmitted to the buffer 11 via the extension node 200. Through an extension transmission line 2, the node 200 is connected to the transmission line 1 on branch basis. Then, the nose 100 performs frame synchronization between data in the buffer 11 and data on the transmission line 1 and then changes a switch 12 from the transmission line side 1 over to the buffer side 1 once completing the synchronization. This system eliminates the occurrence of a data error due to a step out in loop-back operation, performing the extremely smooth extension.

公开(公告)号：JPS5692569A

公开(公告)日：1981-07-27

申请号：JP16985479

申请日：1979-12-26

Applicant: FUJITSU LTD

Inventor： NOJIMA SATOSHI ,  SHINKI TAKASHI

IPC: G06F3/153 ,  G06F3/14 ,  G06G7/20 ,  G06T11/20 ,  G09F1/06 ,  G09G5/20