公开(公告)号：US20230088425A1

公开(公告)日：2023-03-23

申请号：US17483104

申请日：2021-09-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ephrem G. Gebreselasie ,  Steven M. Shank ,  Alain F. Loiseau ,  Robert J. Gauthier, JR. ,  Michel J. Abou-Khalil ,  Ahmed Y. Ginawi

IPC: H01L27/06 ,  H01L21/8234 ,  H01L23/525

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an eFuse and gate structure on a triple-well and methods of manufacture. The structure includes: a substrate comprising a bounded region; a gate structure formed within the bounded region; and an eFuse formed within the bounded region and electrically connected to the gate structure.

公开(公告)号：US20220320073A1

公开(公告)日：2022-10-06

申请号：US17808647

申请日：2022-06-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Robert J. Gauthier, JR. ,  Alain F. Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  Meng Miao ,  You Li

IPC: H01L27/02

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a triple well structure within a semiconductor substrate. A base region is within a doped well of the triple well structure, a collector terminal is within the doped well and laterally separated from the base region by a first insulator and a first avalanche junction is defined between a first pair of oppositely-doped semiconductor regions within the collector terminal. An emitter terminal is within the third doped well of the triple well structure and laterally separated from the collector terminal by a second insulator. A second avalanche junction is defined between a second pair of oppositely-doped semiconductor regions of the emitter terminal.

公开(公告)号：US11289471B2

公开(公告)日：2022-03-29

申请号：US17001009

申请日：2020-08-24

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： You Li ,  Alain F. Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  Robert J. Gauthier, Jr. ,  Meng Miao

IPC: H01L29/74 ,  H01L27/02 ,  H01L29/73 ,  H01L27/06 ,  H01L27/092 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an electrostatic discharge (ESD) device and methods of manufacture. The structure (ESD device) includes: a trigger collector region having fin structures of a first dopant type, a collector region having fin structures in a well of a second dopant type and further including a lateral ballasting resistance; an emitter region having a well of the second dopant type and fin structures of the first dopant type; and a base region having a well and fin structures of the second dopant type.

公开(公告)号：US11201466B2

公开(公告)日：2021-12-14

申请号：US16033731

申请日：2018-07-12

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： You Li ,  Alain F. Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  Mickey Yu ,  Robert J. Gauthier, Jr.

IPC: H02H9/04 ,  H01H1/00 ,  H01L23/60 ,  H01L27/02 ,  H02H1/00

Abstract: A circuit structure includes: a network of clamps; sense elements in series with the clamps and configured to sense a turn-on of at least one clamp of the network of clamps; and feedback elements connected to the clamps to facilitate triggering of remaining clamps of the network of clamps.

公开(公告)号：US20250086657A1

公开(公告)日：2025-03-13

申请号：US18463668

申请日：2023-09-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Peter T. Coutu ,  Romain H.A. Feuillette ,  Alain F. Loiseau

IPC: G06Q30/018 ,  G06K7/14

Abstract: A system and computerized method verify product custody along a product manufacturing chain. The method may include verifying a first machine-readable (MR) code for a product level N is valid by comparing the first MR code to a database of valid MR codes. Where the first MR code for the product level N is verified as valid, a second, valid MR code is generated for a next product level N+1 in the database of valid MR codes. In addition, the first MR code for the product level N in the database of valid MR codes is invalidated, so it cannot be used again. The second MR code is formed for use with the next product level N+1, e.g., by the downstream product manufacturer. Custody of product levels along a manufacturing chain can be verified and secured, avoiding bad actors from inserting and profiting from fake parts into the manufacturing chain.

公开(公告)号：US12068308B2

公开(公告)日：2024-08-20

申请号：US17808647

申请日：2022-06-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Robert J. Gauthier, Jr. ,  Alain F. Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  Meng Miao ,  You Li

IPC: H01L27/02

CPC classification number: H01L27/0259 ,  H01L27/0255

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a triple well structure within a semiconductor substrate. A base region is within a doped well of the triple well structure, a collector terminal is within the doped well and laterally separated from the base region by a first insulator and a first avalanche junction is defined between a first pair of oppositely-doped semiconductor regions within the collector terminal. An emitter terminal is within the third doped well of the triple well structure and laterally separated from the collector terminal by a second insulator. A second avalanche junction is defined between a second pair of oppositely-doped semiconductor regions of the emitter terminal.

公开(公告)号：US12057444B2

公开(公告)日：2024-08-06

申请号：US17808364

申请日：2022-06-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Souvick Mitra ,  Alain F. Loiseau ,  Robert J. Gauthier, Jr. ,  Meng Miao ,  Anindya Nath ,  Wei Liang

IPC: H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/7436

Abstract: A structure includes trigger control circuitry for an SCR including: a first transistor having two P-type semiconductor terminals connected to an Nwell and a Pwell of the SCR; a second transistor having two N-type semiconductor terminals connected to the Pwell and ground; and, optionally, an additional transistor having two P-type semiconductor terminals connected to the Nwell and ground. Control terminals of the transistors receive the same control signal (e.g., RST from a power-on-reset). When a circuit connected to the SCR for ESD protection is powered on, ESD risk is limited so RST switches to high. Thus, the first transistor and optional additional transistor turn off and the second transistor turns on, reducing leakage. When the circuit is powered down, the ESD risk increases so RST switches to low. Thus, the first transistor and optional additional transistor turn on and the second transistor turns off, lowering the trigger voltage and current.

公开(公告)号：US20240234305A1

公开(公告)日：2024-07-11

申请号：US18150831

申请日：2023-01-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh M. Pandey ,  Anindya Nath ,  Alain F. Loiseau ,  Souvick Mitra ,  Chung F. Tan ,  Judson R. Holt

IPC: H01L23/525 ,  H01L23/34 ,  H01L23/62

CPC classification number: H01L23/5256 ,  H01L23/345 ,  H01L23/62

Abstract: A structure includes: an electrically programmable fuse (e-fuse) including an anode and a cathode; at least one transistor positioned adjacent the e-fuse; and an electrically conductive interconnect coupling the cathode of the e-fuse to the at least one transistor, wherein the at least one transistor includes at least one semiconductor fin extending perpendicularly to the e-fuse.

公开(公告)号：US20240063212A1

公开(公告)日：2024-02-22

申请号：US17890725

申请日：2022-08-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Alain F. Loiseau ,  Souvick Mitra ,  Rajendran Krishnasamy

IPC: H01L27/02 ,  H01L29/73 ,  H01L29/735 ,  H01L29/739

CPC classification number: H01L27/0255 ,  H01L29/7302 ,  H01L29/735 ,  H01L29/7393 ,  H01L27/0259

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a diode over a lateral bipolar transistor. A structure according to the disclosure may include a lateral bipolar transistor within a monocrystalline semiconductor over a substrate. An insulator layer is over a portion of the monocrystalline semiconductor. A diode is within a polycrystalline semiconductor on the insulator layer. A cathode of the diode is coupled to a first well within the monocrystalline semiconductor. The first well defines one of an emitter terminal and a collector terminal of the lateral bipolar transistor.

公开(公告)号：US11444076B2

公开(公告)日：2022-09-13

申请号：US16983071

申请日：2020-08-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Robert J. Gauthier, Jr. ,  Alain F. Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  Meng Miao ,  You Li

IPC: H01L27/02

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a doped well in a semiconductor substrate, in addition to a base region, emitter region, and collector region in the doped well. An insulative material is within the doped well, with a first end horizontally adjacent the collector region and a second end opposite the first end. A doped semiconductor region is within the doped well adjacent the second end of the insulative material. The doped semiconductor region is positioned to define an avalanche junction between the collector region and the doped semiconductor region across the doped well.