公开(公告)号：GB2422487B

公开(公告)日：2007-05-02

申请号：GB0607210

申请日：2003-09-23

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: G06K19/073 ,  H01L23/58

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.

公开(公告)号：GB2405531B

公开(公告)日：2006-04-12

申请号：GB0427115

申请日：2003-05-06

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  BAUKUS JAMES P

IPC: H01L21/331 ,  H01L27/02 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8247 ,  H01L23/58 ,  H01L27/04 ,  H01L27/092 ,  H01L27/115 ,  H01L29/732 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

公开(公告)号：GB2412240A

公开(公告)日：2005-09-21

申请号：GB0512203

申请日：2005-06-15

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK JR WILLIAM M ,  BAUKUS JAMES P ,  HARBISON GAVIN J

IPC: H01L21/8238 ,  H01L27/02 ,  H01L29/76

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.

公开(公告)号：GB2391986A8

公开(公告)日：2005-06-15

申请号：GB0325521

申请日：2002-03-12

Applicant: HRL LAB LLC

Inventor： CLARK WILLIAM M JR ,  CHOW LAP-WAI ,  BAUKUS JAMES P

IPC: G11C17/18 ,  G06F12/14 ,  G11C7/12 ,  G11C7/18 ,  G11C7/24 ,  G11C16/02 ,  G11C16/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/10 ,  H01L27/112 ,  H01L27/115

Abstract: A method and circuit for blocking unauthorized access to at least one memory cell in a semiconductor memory. The method includes providing a switch and/or a link which assumes an open state when access to the at least one memory cell is to be blocked; and coupling-a data line associated with the at least one memory cell to a constant voltage source in response to the switch or link assuming an open state.

公开(公告)号：AU2003284270A8

公开(公告)日：2004-05-13

申请号：AU2003284270

申请日：2003-10-16

Applicant: PROMTEK ,  HRL LAB LLC

Inventor： BAUKUS JAMES P ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  YANG PAUL OU

IPC: H01L23/04 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L27/02 ,  H01L29/40

Abstract: A multilayered integrated circuit and a method of designing a multilayered integrated circuit are provided. The circuit comprises at least two conductive layers and extraneous conductive lines placed in the conductive layers. The extraneous conductive lines are made of a material which is the same as the material in the conductive layers and have dimensions which are the same as the dimension of the material in the conductive layers. The extraneous conductive lines perform functions which are unnecessary to the operation of the integrated circuit and are undistinguishable from the functional conductive lines, thus burdening the work of a reverse engineer. The method of designing the multilayered circuit comprises a step of providing a computer generated representation of the extraneous conductive lines.

公开(公告)号：GB2430800A

公开(公告)日：2007-04-04

申请号：GB0622262

申请日：2003-11-20

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: H01L27/02 ,  H01L23/58

Abstract: The spacing between the source/drain and gate electrodes of a non-operable MOSFET is set to a distance equal to a sidewall spacer to increase the similarity between non-operable and operable devices. The device structure inhibits attempts at reverse engineering.

公开(公告)号：GB2410835B

公开(公告)日：2007-01-17

申请号：GB0508291

申请日：2003-09-23

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: G06K19/073 ,  H01L23/58

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.

公开(公告)号：GB2422956A

公开(公告)日：2006-08-09

申请号：GB0608053

申请日：2003-11-20

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: H01L27/02 ,  H01L23/58

Abstract: The distance between the gate and source/drain of a non-operable FET is defined by a block mask to be the same as the distance between the gate and source/drain of an operable FET which is defined by a gate sidewall spacer. The camouflaged non-operable circuit structure inhibits attempts at reverse engineering.

公开(公告)号：GB2411293B

公开(公告)日：2006-07-12

申请号：GB0510347

申请日：2003-10-16

Applicant: HRL LAB LLC ,  PROMTEK

Inventor： BAUKUS JAMES P ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  YANG PAUL OU

IPC: H01L27/02 ,  H01L23/04 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L29/40

Abstract: A multilayered integrated circuit and a method of designing a multilayered integrated circuit are provided. The circuit comprises at least two conductive layers and extraneous conductive lines placed in the conductive layers. The extraneous conductive lines are made of a material which is the same as the material in the conductive layers and have dimensions which are the same as the dimension of the material in the conductive layers. The extraneous conductive lines perform functions which are unnecessary to the operation of the integrated circuit and are undistinguishable from the functional conductive lines, thus burdening the work of a reverse engineer. The method of designing the multilayered circuit comprises a step of providing a computer generated representation of the extraneous conductive lines.

公开(公告)号：GB2413436A

公开(公告)日：2005-10-26

申请号：GB0511670

申请日：2003-11-20

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK JR WILLIAM M ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: H01L23/58 ,  H01L27/02

Abstract: A technique for and structres for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.