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    CMOS PROCESS
    4.
    发明申请
    CMOS PROCESS 审中-公开
    CMOS工艺

    公开(公告)号：WO02103785A3

    公开(公告)日：2003-08-14

    申请号：PCT/US0219074

    申请日：2002-06-13

    Applicant: HRL LAB LLC ,  BAUKUS JAMES P ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

    Inventor： BAUKUS JAMES P ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

    IPC: H01L21/768 ,  H01L27/02 ,  H01L21/8234 ,  H01L23/58 ,  H01L27/088

    CPC classification number: H01L27/02 ,  H01L21/76895 ,  H01L27/0203

    Abstract: An integrated circuit structure for MOS-type devices comprising a silicon substrate of a first conductivity type; a first gate insulating regions selectivelyplaced over the silicon substrate of the first conductivity type; a first polycrystallinesilicon layer selectively placed over the silicon substrate of the first conductivity type;a second gate insulating regions selectively placed over the first gate insulating regionsand the first polycrystalline silicon layer; a second polycrystalline silicon layer selectivelyplaced over the second gate insulating regions; first buried silicon regions of a second conductivity type, buried within the silicon substrate of the first conductivity type, placedunder the first polycrystalline silicon layer and in contact therewith; and second buriedsilicon regions of the second conductivity type, buried within the silicon substrate of the first conductivity type, placed under the second gate insulating regions, under the secondpolycrystalline silicon layer and insulated therefrom.

    Abstract translation: 一种用于MOS器件的集成电路结构，包括第一导电类型的硅衬底; 选择性地放置在第一导电类型的硅衬底上的第一栅绝缘区; 选择性地放置在第一导电类型的硅衬底上的第一多晶硅层;选择性地放置在第一栅极绝缘区域和第一多晶硅层上的第二栅极绝缘区域; 选择性地放置在第二栅绝缘区上的第二多晶硅层; 第一导电类型的第一掩埋硅区域，埋在第一导电类型的硅衬底内，放置在第一多晶硅层之下并与其接触; 以及第二导电类型的第二掩埋硅区域，其被埋置在第二导电类型的硅衬底内，放置在第二栅极绝缘区域下方，在第二多晶硅层下方并与其绝缘。

    Integrated circuit to inhibit reverse engineering
    7.
    发明专利
    Integrated circuit to inhibit reverse engineering 未知

    公开(公告)号：GB2422487A

    公开(公告)日：2006-07-26

    申请号：GB0607210

    申请日：2003-09-23

    Applicant: HRL LAB LLC ,  RAYTHEON CO

    Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

    IPC: G06K19/073 ,  H01L23/58

    Abstract: An integrated circuit is protected from reverse engineering by providing conducting and non-conducting channels which appear identical. Active regions 22, 26 are connected by channel areas 23, 25 and pseudo channel-block structure 29 all of the same conductivity type. A layer of metal silicide is disposed over the active regions 22, 26 and channel areas 23, 25 but not the pseudo channel block structure 29. When reverse engineering techniques are applied edge artefacts 28 of the silicide covering a pseudo channel-blocked conducting channel appear identical to those of a non-conducting channel-blocked channel (figure 1B).

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