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公开(公告)号:DE1957788A1
公开(公告)日:1970-05-27
申请号:DE1957788
申请日:1969-11-18
Applicant: IBM
Inventor: HARRY DEPUY ARTHUR , NORMAN KUSCHEL WILLIAM , AGUSTA BENJAMIN , JIT SAHNI RAVINDER
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公开(公告)号:CA992668A
公开(公告)日:1976-07-06
申请号:CA84637
申请日:1970-06-04
Applicant: IBM
Inventor: AGUSTA BENJAMIN , DEWITT DAVID , HESS MARTIN S , PECORARO RAYMOND P
IPC: H01L21/761 , H01L21/8222 , H01L27/00 , H01L29/00 , H01L29/08
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公开(公告)号:CA911055A
公开(公告)日:1972-09-26
申请号:CA911055D
Applicant: IBM
Inventor: BARDELL PAUL H , CASTRUCCI PAUL P , AGUSTA BENJAMIN , HENLE ROBERT A , PECORARO RAYMOND P
IPC: G11C5/04 , G11C11/40 , G11C11/411 , H03K3/286 , H03K3/288
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公开(公告)号:CA892846A
公开(公告)日:1972-02-08
申请号:CA892846D
Applicant: IBM
Inventor: AGUSTA BENJAMIN , SAHNI RAVINDER J
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公开(公告)号:DE1764464A1
公开(公告)日:1971-08-05
申请号:DE1764464
申请日:1968-06-11
Applicant: IBM
Inventor: AGUSTA BENJAMIN , DAVID LUBART NEIL
IPC: H01L21/8224 , H01L27/082 , H01L7/44
Abstract: 1,197,403. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 31 May, 1968 [15 June, 1967], No. 26082/68. Heading H1K. In a monolithic semi-conductor structure comprising a P-type substrate 10 in which is formed an N+type region 18 and there is an epitaxial N-type layer 20 formed over the substrate and the N + type region, and wherein isolating P+type walls 26 extend through the layer to the substrate to electrically isolate areas of the layer, a P + type region 28 extends right through the layer 20 to the N + type region 18 to form the emitter of a first transistor, the adjacent portion of the layer 20 forming the base region of the transistor. A P-type region 38 forms the collector of this first transistor. In a second isolated area a complementary transistor is formed having a P-type base 40 and N+type emitter region 48. A passivating silicon oxide layer 22 covers the surface of the structure and electrodes of aluminium or molybdenum 50, 52, 54 and 56, 58, 60 provide the electrical connections and interconnections. The structure is made of silicon and the dopants used are boron, arsenic and phosphorus. A combined complementary pair of transistors is described, Fig. 4, not shown, where a PNP and NPN transistor are formed in a single isolated region. In alternative configurations of the PNP transistor, Fig. 2, not shown, the P+ type collector extends right through the epitaxial layer into the N+type region in the same way as the emitter to give a symmetrical device. Alternatively, Fig. 3, not shown, one of the P+type isolating walls may be used as the collector.
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