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    Method of forming self-aligned field effect transistor and charge-coupled device
    2.
    发明授权
    Method of forming self-aligned field effect transistor and charge-coupled device 失效
    形成自对准场效应晶体管和电荷耦合器件的方法

    公开(公告)号：US3865652A

    公开(公告)日：1975-02-11

    申请号：US40374573

    申请日：1973-10-05

    Applicant: IBM

    Inventor： AGUSTA BENJAMIN ,  CHANG JOSEPH J ,  JOSHI MADHUKAR L

    IPC: H01L21/00 ,  H01L21/8234 ,  H01L27/105 ,  H01L29/00 ,  H01L29/10 ,  H01L29/423 ,  H01L29/768 ,  H01L7/44

    CPC classification number: H01L29/76866 ,  H01L21/00 ,  H01L21/823406 ,  H01L27/1057 ,  H01L29/00 ,  H01L29/1062 ,  H01L29/42396 ,  Y10S148/053 ,  Y10S148/114 ,  Y10S148/122

    Abstract: A semiconductor device containing in a single semiconductor body a self-aligned Field Effect Transistor and a Charge-Coupled Array having an improved capacity for storing charges. The device is formed by depositing both polysilicon and silicon nitride layers over a silicon dioxide layer on the surface of a silicon body and selectively etching these layers so that suitable dopants may be diffused or ion-implanted into selected areas of the underlying silicon body to form, in the same semiconductor body, an improved charge-coupled array having an improved self-aligned Field Effect Transistor associated therewith. This process not only results in a device in which the chance of an inversion layer under the oxide on the surface of the device is substantially reduced, but also provides a self-aligned Field Effect Transistor having a thinner gate oxide and a charge-coupled array that has an increased capacity for storing charges. The improved array so formed also has, during operation, zero spaced depletion regions so that unwanted electrical discontinuities between or within the depletion regions of the charge-coupled array are avoided. Because zero spacing is achieved by using these thin conducting layers, the metal phase lines can be made narrow thus leaving openings in the charge transfer channel making the device particularly suitable for imaging applications.

    Abstract translation: 一种半导体器件，其在单个半导体本体中包含具有改善的用于存储电荷的容量的自对准场效应晶体管和电荷耦合阵列。 该器件通过在硅体表面上的二氧化硅层上沉积多晶硅和氮化硅层而形成，并且选择性地蚀刻这些层，使得合适的掺杂剂可以扩散或离子注入到下面的硅体的选定区域中以形成 在相同的半导体本体中，改进的电荷耦合阵列具有与其相关联的改进的自对准场效应晶体管。 该方法不仅导致其中在器件表面上的氧化物下面的反型层的机会大大降低的装置，而且还提供具有较薄栅极氧化物和电荷耦合阵列的自对准场效应晶体管 这增加了存储费用的能力。 这样形成的改进的阵列在操作期间还具有零间隔的耗尽区域，从而避免了在电荷耦合阵列的耗尽区域之间或内部的不期望的电中断。 因为通过使用这些薄导电层来实现零间隔，所以可以使金属相线变窄，从而在电荷转移通道中留下开口，使得该器件特别适用于成像应用。

    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE UTILIZING AVALANCHE INJECTION AND EXTRACTION TORED INFORMATION
    7.
    发明专利
    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE UTILIZING AVALANCHE INJECTION AND EXTRACTION TORED INFORMATION 未知

    公开(公告)号：CA1019441A

    公开(公告)日：1977-10-18

    申请号：CA186057

    申请日：1973-11-16

    Applicant: IBM

    Inventor： AGUSTA BENJAMIN ,  CHANG JOSEPH J

    IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

    Abstract: 1445450 Semiconductor data storage INTERNATIONAL BUSINESS MACHINES CORP 29 Nov 1973 [29 Dec 1972] 55360/73 Heading H1K A floating gate data storage FET 10 (Fig. 1) is coupled to conventional word driver 12, bit driver 14, and bit sense amplifier 15; and comprises a semiconductor substrate 16 of, e.g. N-doped Si having opposite conductivity diffused P doped source and drain regions 17, 18 separated by channel region 19. An insulant layer 21 of SiO 2 is formed over the substrate, etched into openings for source and drain diffusion and for the channel, and an oxide layer 24 of thickness to prevent tunnelling with normal I operating voltages is reformed in the channel opening. A gate electrode 25 of semiconductor material devoid of free carriers is deposited on the oxide layer 24 and is encapsulated in insulant 26, e.g. similar to layer 24 so as to float electrically. Contacts 27, 28 are applied to source and drain diffusions 17, 18 and an overlying drive gate electrode 29 is deposited on layer 25. Drain electrode 27 is coupled over 2-piston switch 30 to bit driver 14 and sense amplifier 15 or to earth, while source electrode 28 and substrate 16 are both earthed. Drive gate 29 is connected to word driver 12. Gate 25 may consume excess charge to create conductively a channel between source 17 and drain 18 to represent logic "1"; logic "0" being denoted by its absence. For logic "1" write in, the drain electrode 27 is switched to the bit driver 14 and sense amplifier 15 and the former is driven to produce ave pulse (Fig. 2 not shown) on the drain to backbias region 18, and a + ve pulse is applied to the gate electrode 29 from the word driver 12. Avalanche breakdown between drain region 18 and substrate 16 proximate to region 19 generates high energy electrons beneath the floating gate which pass thereto through layer 24 under influence of the prevailing electric fields and are stored. The accumulated electrons induce a channel between source and drain diffusions 17, 18 and the existence or non- existence of the source denotes the presence or absence of this electron charge. Low level read pulses on drain electrode 27 and drive gate electrode 29 enable detection of stored charge by the appearance of pulses on the sense amplifier 15. Charge is removed from the floating gate 25 to eliminate the induced channel and erase the storage by setting switch 30 to earth and negatively pulsing drive gate 29 from the word driver 12 so as to deplete the floating gate by avalanche breakedown into region 19. Plural short pulses may be used for erasure.

    8.
    发明专利
    未知

    公开(公告)号：DE2356275A1

    公开(公告)日：1974-07-04

    申请号：DE2356275

    申请日：1973-11-10

    Applicant: IBM

    Inventor： AGUSTA BENJAMIN ,  CHANG JOSEPH JUIFU

    IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40 ,  G11C7/00

    Abstract: 1445450 Semiconductor data storage INTERNATIONAL BUSINESS MACHINES CORP 29 Nov 1973 [29 Dec 1972] 55360/73 Heading H1K A floating gate data storage FET 10 (Fig. 1) is coupled to conventional word driver 12, bit driver 14, and bit sense amplifier 15; and comprises a semiconductor substrate 16 of, e.g. N-doped Si having opposite conductivity diffused P doped source and drain regions 17, 18 separated by channel region 19. An insulant layer 21 of SiO 2 is formed over the substrate, etched into openings for source and drain diffusion and for the channel, and an oxide layer 24 of thickness to prevent tunnelling with normal I operating voltages is reformed in the channel opening. A gate electrode 25 of semiconductor material devoid of free carriers is deposited on the oxide layer 24 and is encapsulated in insulant 26, e.g. similar to layer 24 so as to float electrically. Contacts 27, 28 are applied to source and drain diffusions 17, 18 and an overlying drive gate electrode 29 is deposited on layer 25. Drain electrode 27 is coupled over 2-piston switch 30 to bit driver 14 and sense amplifier 15 or to earth, while source electrode 28 and substrate 16 are both earthed. Drive gate 29 is connected to word driver 12. Gate 25 may consume excess charge to create conductively a channel between source 17 and drain 18 to represent logic "1"; logic "0" being denoted by its absence. For logic "1" write in, the drain electrode 27 is switched to the bit driver 14 and sense amplifier 15 and the former is driven to produce ave pulse (Fig. 2 not shown) on the drain to backbias region 18, and a + ve pulse is applied to the gate electrode 29 from the word driver 12. Avalanche breakdown between drain region 18 and substrate 16 proximate to region 19 generates high energy electrons beneath the floating gate which pass thereto through layer 24 under influence of the prevailing electric fields and are stored. The accumulated electrons induce a channel between source and drain diffusions 17, 18 and the existence or non- existence of the source denotes the presence or absence of this electron charge. Low level read pulses on drain electrode 27 and drive gate electrode 29 enable detection of stored charge by the appearance of pulses on the sense amplifier 15. Charge is removed from the floating gate 25 to eliminate the induced channel and erase the storage by setting switch 30 to earth and negatively pulsing drive gate 29 from the word driver 12 so as to deplete the floating gate by avalanche breakedown into region 19. Plural short pulses may be used for erasure.

    10.
    发明专利
    未知

    公开(公告)号：DE2314260A1

    公开(公告)日：1973-12-13

    申请号：DE2314260

    申请日：1973-03-22

    Applicant: IBM

    Inventor： CHANG JOSEPH JUIFU ,  JOSHI MADHUKAR LAXMAN ,  AGUSTA BENJAMIN

    IPC: H01L21/00 ,  H01L21/8234 ,  H01L27/105 ,  H01L29/00 ,  H01L29/10 ,  H01L29/423 ,  H01L29/768 ,  H01L13/00

    Abstract: A semiconductor device containing in a single semiconductor body a self-aligned Field Effect Transistor and a Charge-Coupled Array having an improved capacity for storing charges. The device is formed by depositing both polysilicon and silicon nitride layers over a silicon dioxide layer on the surface of a silicon body and selectively etching these layers so that suitable dopants may be diffused or ion-implanted into selected areas of the underlying silicon body to form, in the same semiconductor body, an improved charge-coupled array having an improved self-aligned Field Effect Transistor associated therewith. This process not only results in a device in which the chance of an inversion layer under the oxide on the surface of the device is substantially reduced, but also provides a self-aligned Field Effect Transistor having a thinner gate oxide and a charge-coupled array that has an increased capacity for storing charges. The improved array so formed also has, during operation, zero spaced depletion regions so that unwanted electrical discontinuities between or within the depletion regions of the charge-coupled array are avoided. Because zero spacing is achieved by using these thin conducting layers, the metal phase lines can be made narrow thus leaving openings in the charge transfer channel making the device particularly suitable for imaging applications.

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