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公开(公告)号：BR9102128A
公开(公告)日：1991-12-24
申请号：BR9102128
申请日：1991-05-24
Applicant: IBM
Inventor： EICHEMEYER RICHARD J , VASSILIADIS STAMATIS , BLANER BARTHOLOMEW
Abstract: A digital computer system is described capable of processing two or more computer instructions in parallel and having a main memory unit for storing information blocks including the computer instructions includes an instruction compounding unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with another neighboring instruction. Tagged instructions are stored in the main memory. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to the functional units are obtained from the memory by way of a cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
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公开(公告)号：CS93691A2
公开(公告)日：1991-12-17
申请号：CS93691
申请日：1991-04-04
Applicant: IBM
Inventor： BLANER BARTHOLOMEW , VASSILIADIS STAMATIS
Abstract: Described is a scalable compound instruction set machine and method which provides for processing a set of instructions or program to be executed by a computer to determine statically which instructions may be combined into compound instructions which are executed in parallel by a scalar machine. Such processing looks for classes of instructions that can be executed in parallel without data-dependent or hardware-dependent interlocks. Without regard to their original sequence the individual instructions are combined with one or more other individual instructions to form a compound instruction which eliminates interlocks. Control information is appended to identify information relevant to the execution of the compound instructions. The result is a stream of scalar instructions compounded or grouped together before instruction decode time so that they are already flagged and identified for selective simultaneous parallel execution by execution units. The compounding does not change the object code results and existing programs realize performance improvements while maintaining compatibility with previously implemented systems for which the original set of instructions was provided.
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公开(公告)号：HUT57454A
公开(公告)日：1991-11-28
申请号：HU109991
申请日：1991-04-04
Applicant: IBM
Inventor： BLANER BARTHOLOMEW , VASSILIADIS STAMATIS
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公开(公告)号：HU911099D0
公开(公告)日：1991-10-28
申请号：HU109991
申请日：1991-04-04
Applicant: IBM
Inventor： BLANER BARTHOLOMEW , VASSILIADIS STAMATIS
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公开(公告)号：DE112012004727T5
公开(公告)日：2014-07-31
申请号：DE112012004727
申请日：2012-09-27
Applicant: IBM
Inventor： REILLY JOHN J , ABALI BULENT , BLANER BARTHOLOMEW
IPC: H03D3/24
Abstract: Bereitgestellt wird ein Entpacken einer variablen Anzahl von Datenbits. Eine Struktur enthält den Eingangsanschluss 15, der ausführbar ist, um eine oder mehrere Eingabedateneinheiten zu empfangen, die eine Vielzahl von gepackten Datenbits enthalten, wobei jede der einen oder der mehreren Eingabedateneinheiten einen Header und Nutzdaten enthält, wobei der Header eine vordefinierte Anzahl von Bits enthält und ein Format der Nutzdaten und eine Länge der Nutzdaten identifiziert, und wobei die Nutzdaten eine variable Anzahl von Bits enthalten. Die Struktur enthält ferner eine Schaltung, die ausführbar ist, um die eine oder die mehreren Eingabedateneinheiten auf der Grundlage des Headers und der Nutzdaten von jeder der einen oder der mehreren Eingabedateneinheiten zu identifizieren und zu entpacken. Die Struktur enthält ferner den Ausgangsanschluss 20, der ausführbar ist, um eine oder mehrere Ausgabedateneinheiten, welche die entpackte eine oder die entpackten mehreren Eingabedateneinheiten enthalten, einmal pro Taktzyklus zu übertragen,
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Patent Agency Ranking
公开(公告)号：AT189540T
公开(公告)日：2000-02-15
申请号：AT91105248
申请日：1991-04-03
Applicant: IBM
Inventor： VASSILIADIS STAMATIS , BLANER BARTHOLOMEW
Abstract: A digital computer system is described capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and generating for to each instruction a compounding information which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit with the compounding information. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit. At instruction issue time, the compounding information for the instructions is examined and those instructions indicated for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
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公开(公告)号：DE69229198T2
公开(公告)日：1999-12-09
申请号：DE69229198
申请日：1992-03-13
Applicant: IBM
IPC: G06F9/38
Abstract: The parallelism of a multi-pipelined digital computer is enhanced by detection of branch instructions from the execution pipelines and concurrent processing of up to two of the detected instructions in parallel with the operations of the execution pipelines. Certain branch instructions, when detected, are removed altogether from the pipeline, but still processed. The processing is synchronized with the execution pipeline to, first, predict an outcome for detected branch instructions, second, test the conditions for branch instructions at their proper place in the execution sequence to determine whether the predicted outcome was correct, and third, fetch a corrected target instruction if the prediction proves wrong.
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公开(公告)号：DE69229198D1
公开(公告)日：1999-06-24
申请号：DE69229198
申请日：1992-03-13
Applicant: IBM
IPC: G06F9/38
Abstract: The parallelism of a multi-pipelined digital computer is enhanced by detection of branch instructions from the execution pipelines and concurrent processing of up to two of the detected instructions in parallel with the operations of the execution pipelines. Certain branch instructions, when detected, are removed altogether from the pipeline, but still processed. The processing is synchronized with the execution pipeline to, first, predict an outcome for detected branch instructions, second, test the conditions for branch instructions at their proper place in the execution sequence to determine whether the predicted outcome was correct, and third, fetch a corrected target instruction if the prediction proves wrong.
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公开(公告)号：DE69123629T2
公开(公告)日：1997-06-12
申请号：DE69123629
申请日：1991-03-20
Applicant: IBM
Inventor： BLANER BARTHOLOMEW , VASSILIADIS STAMATIS
Abstract: Described is a scalable compound instruction set machine and method which provides for processing a set of instructions or program to be executed by a computer to determine statically which instructions may be combined into compound instructions which are executed in parallel by a scalar machine. Such processing looks for classes of instructions that can be executed in parallel without data-dependent or hardware-dependent interlocks. Without regard to their original sequence the individual instructions are combined with one or more other individual instructions to form a compound instruction which eliminates interlocks. Control information is appended to identify information relevant to the execution of the compound instructions. The result is a stream of scalar instructions compounded or grouped together before instruction decode time so that they are already flagged and identified for selective simultaneous parallel execution by execution units. The compounding does not change the object code results and existing programs realize performance improvements while maintaining compatibility with previously implemented systems for which the original set of instructions was provided.
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公开(公告)号：DE69115344T2
公开(公告)日：1996-06-20
申请号：DE69115344
申请日：1991-03-20
Applicant: IBM
Inventor： BLANER BARTHOLOMEW , VASSILIADIS STAMATIS
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