公开(公告)号：SK93491A3

公开(公告)日：1995-09-13

申请号：SK93491

申请日：1991-04-04

Applicant: IBM

Inventor： BLANER BARTHOLOMEW ,  VASSILIADIS STAMATIS ,  EICHEMEYER RICHARD J

IPC: G06F15/00 ,  G06F9/00 ,  G06F9/38 ,  G06F13/38 ,  G06F13/00

Abstract: A digital computer system is described capable of processing two or more computer instructions in parallel and having a main memory unit for storing information blocks including the computer instructions includes an instruction compounding unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with another neighboring instruction. Tagged instructions are stored in the main memory. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to the functional units are obtained from the memory by way of a cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.

公开(公告)号：BR9102128A

公开(公告)日：1991-12-24

申请号：BR9102128

申请日：1991-05-24

Applicant: IBM

Inventor： EICHEMEYER RICHARD J ,  VASSILIADIS STAMATIS ,  BLANER BARTHOLOMEW

IPC: G06F15/00 ,  G06F9/00 ,  G06F9/38 ,  G06F13/38 ,  G06F15/20

Abstract: A digital computer system is described capable of processing two or more computer instructions in parallel and having a main memory unit for storing information blocks including the computer instructions includes an instruction compounding unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with another neighboring instruction. Tagged instructions are stored in the main memory. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to the functional units are obtained from the memory by way of a cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.