公开(公告)号：CA1191268A

公开(公告)日：1985-07-30

申请号：CA414119

申请日：1982-10-25

Applicant: IBM

Inventor： BREZZO BERNARD ,  CALVIGNAC JEAN ,  DAMBRICOURT RICHARD ,  MASCLET ANDRE ,  SANCHE JEAN-PIERRE

IPC: H04L69/14 ,  G06F13/00 ,  G06F13/38 ,  G06F13/22

Abstract: A COMMUNICATION LINE SCANNING DEVICE FOR A COMMUNICATION CONTROLLER A line scanning device for the line adapter of a communication controller comprises three memories addressable by an address select and control device which sequentially generates the address of the lines to be scanned on line and the addresses of the memories and read/write control signals. The memories are associated to two logic circuits. One circuit is connected to the lines to be scanned and the other is connected to a microprocessor associated with the scanning device. In each memory, location areas are assigned to each line. The message is processed in assembly at the bit level and in assembly at the character level. The exchange operation with the microprocessor is performed in cycle steal mode between assembly and the microprocessor control memory.

公开(公告)号：AU8979282A

公开(公告)日：1983-06-16

申请号：AU8979282

申请日：1982-10-26

Applicant: IBM

Inventor： BREZZO BERNARD ,  CALVIGNAC JEAN ,  MASCLET ANDRE ,  SANCHE JEAN-PIERRE

IPC: H04L69/14 ,  G06F13/00 ,  G06F13/38 ,  G06F3/04 ,  H04L11/20

Abstract: A line scanning device which operates under the control of a microprocessor connected to a control memory in which a memory location area is assigned to each line is provided for a line adapter in a communication controller for receiving or sending message bits in series from or to terminals connected to the lines using any protocols. It comprises a first store which includes a first and a second memories, an area being assigned to each line in each of the memories which can be read and written in the same time and a second store which includes a single memory in which a storage location area is assigned to each line. These stores are addressed by a control and address unit which includes first and second address counters under the control of an elementary time counter, the first counter outputting the address information relating to the first store during time t provided for scanning a line, and the second counter outputting the address information relative to the second store during time nt, n being at least equal to 4, and control circuitry receiving said address information and the elementary time information for providing at the outputs of the control and address unit, memory address and read/write control information at times selected during the scanning period and sequentially, the addresses of the present lines which are scanned.