公开(公告)号：DE69522267D1

公开(公告)日：2001-09-27

申请号：DE69522267

申请日：1995-02-03

Applicant: IBM

Inventor： FERRAIOLO FRANK DAVID ,  CAPOWSKI ROBERT STANLEY ,  CASPER DANIEL FRANCIS ,  JORDAN RICHARD CARROLL ,  LAVIOLA WILLIAM CONSTANTINO

IPC: G06F13/42 ,  H04L7/00 ,  H04L7/033 ,  G06F13/40

Abstract: A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individualy phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.

公开(公告)号：DE69022359T2

公开(公告)日：1996-03-28

申请号：DE69022359

申请日：1990-10-10

Applicant: IBM

Inventor： CASPER DANIEL FRANCIS ,  FLANAGAN JOHN RICHARD ,  GREGG THOMAS ANTHONY ,  HUANG CATHERINE CHE-WEN ,  KALOS MATTHEW JOSEPH

IPC: H04J3/06 ,  H04L7/00 ,  H04L7/02 ,  H04L7/04 ,  H04L7/08

公开(公告)号：CA2150744A1

公开(公告)日：1995-12-18

申请号：CA2150744

申请日：1995-06-01

Applicant: IBM

Inventor： FERRAIOLO FRANK DAVID ,  CAPOWSKI ROBERT STANLEY ,  CASPER DANIEL FRANCIS ,  JORDAN RICHARD CARROLL ,  LAVIOLA WILLIAM CONSTANTINO

IPC: G06F13/42 ,  H04L7/00 ,  H04L7/033

Abstract: A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individualy phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.

公开(公告)号：CA2821233C

公开(公告)日：2020-05-05

申请号：CA2821233

申请日：2012-05-03

Applicant: IBM

Inventor： HATHORN ROGER ,  FLANAGAN JOHN ,  RICCI LOUIS ,  CARLSON SCOTT ,  KALOS MATTHEW JOSEPH ,  YUDENFRIEND HARRY ,  RIEDY DALE ,  CASPER DANIEL FRANCIS ,  CANDELARIA SUSAN KAY

IPC: G06F13/12

Abstract: A computer program product is configured for performing a method including: generating at least one command message by a channel subsystem of the host computer system, the at least one command message including one or more device command words (DCWs), wherein at least one DCW of the one or more DCWs includes a suppress-length indication (SLI) configured to instruct a control unit to continue to perform the I/O operation in response to the control unit detecting that the data count does not match an amount of data required; receiving an incorrect length (IL) value, the IL value being a first IL value in response to the SLI being a first SLI value and the data count not matching the amount of data required; and responsive to receiving the IL value from the control unit, storing an IL indicator in a subchannel-status word.

公开(公告)号：GB2505140B

公开(公告)日：2014-06-04

申请号：GB201321837

申请日：2012-05-21

Applicant: IBM

Inventor： FLANAGAN JOHN ,  TURNER JEFFREY ,  BUBB CLINTON ,  CASPER DANIEL FRANCIS ,  KUCH GEORGE PETER ,  HIGGS RAYMOND MICHAEL

IPC: G06F13/38

公开(公告)号：PL2593878T3

公开(公告)日：2014-05-30

申请号：PL12716322

申请日：2012-04-11

Applicant: IBM

Inventor： HATHORN ROGER ,  FLANAGAN JOHN ,  RICCI LOUIS WILLIAM ,  CARLSON SCOTT ,  KALOS MATTHEW JOSEPH ,  YUDENFRIEND HARRY ,  RIEDY DALE ,  CASPER DANIEL FRANCIS

IPC: G06F13/42

公开(公告)号：GB2491439B

公开(公告)日：2013-05-15

申请号：GB201206683

申请日：2012-04-17

Applicant: IBM

Inventor： CASPER DANIEL FRANCIS ,  FLANAGAN JOHN R ,  BUBB CLINTON

IPC: G06F13/42 ,  G06F13/12

Abstract: A method of performing an input/output (I/O) processing operation includes: generating an address control structure for each of a plurality of consecutive data transfer requests, each address control structure specifying a local channel memory location of a corresponding address control word (ACW); receiving a data transfer request from a network interface that includes addressing information specified by a corresponding address control structure; comparing, by a data router in the channel, an Offset field of an address control structure and an Expected Offset field of an ACW to determine whether the data transfer request has been received in the correct order; and based on determining that the data transfer request has been received in the correct order, accessing the ACW by the data router and routing the data transfer request to a host memory location specified in the ACW.

公开(公告)号：CA2821233A1

公开(公告)日：2013-01-03

申请号：CA2821233

申请日：2012-05-03

Applicant: IBM

Inventor： HATHORN ROGER ,  FLANAGAN JOHN ,  RICCI LOUIS ,  CARLSON SCOTT ,  KALOS MATTHEW JOSEPH ,  YUDENFRIEND HARRY ,  RIEDY DALE ,  CASPER DANIEL FRANCIS ,  CANDELARIA SUSAN KAY

IPC: G06F13/12

Abstract: A computer program product is configured for performing a method including: generating at least one command message by a channel subsystem of the host computer system, the at least one command message including one or more device command words (DCWs), wherein at least one DCW of the one or more DCWs includes a suppress-length indication (SLI) configured to instruct a control unit to continue to perform the I/O operation in response to the control unit detecting that the data count does not match an amount of data required; receiving an incorrect length (IL) value, the IL value being a first IL value in response to the SLI being a first SLI value and the data count not matching the amount of data required; and responsive to receiving the IL value from the control unit, storing an IL indicator in a subchannel-status word.

公开(公告)号：GB2491437A

公开(公告)日：2012-12-05

申请号：GB201206681

申请日：2012-04-17

Applicant: IBM

Inventor： CASPER DANIEL FRANCIS ,  FLANAGAN JOHN R ,  BUBB CLINTON

IPC: G06F13/12 ,  G06F13/38

Abstract: A method for performing an input/output (I/O) operation between a host computer (102) and control-unit (118) comprises obtaining information about the I/O operation from a channel subsystem (128) in the host system, the channel having a local processor and memory. An Address Control Word (ACW) (Fig 11) is generated and specifying the memory location and including a field for storing header information for use in one or more messages transmitted between the channel subsystem and the control unit. An address control structure (Fig 5) for each data transfer in the I/O operation is generated and forwarded to the network interface between the channel subsystem and I/O device and specifies a location in the local memory of the ACW. On receipt of an I/O command message via the network a data transfer request from the network interface is issued and includes addressing information. In response to a data store request including a header the data is routed to the memory location stored in the ACW and the header stored in the corresponding ACW. In response to a data read request including a header the data is retrieved from the host memory location specified in the ACW and header information is appended to the data.

公开(公告)号：GB2491436A

公开(公告)日：2012-12-05

申请号：GB201206680

申请日：2012-04-17

Applicant: IBM

Inventor： CASPER DANIEL FRANCIS ,  FLANAGAN JOHN R ,  BUBB CLINTON

IPC: G06F13/12 ,  G06F13/38 ,  G06F13/42 ,  G06F21/00

Abstract: A method for performing an input/output (I/O) operation between a host computer (102) and control-unit (118) comprises obtaining information about the I/O operation from a channel subsystem (128) in the host system, the channel having a local processor and memory. An Address Control Word (ACW) (Fig 11) is generated and specifying the memory location and having an error checking field is stored in the local memory. An address control structure (Fig 5) for each data transfer in the I/O operation is generated and forwarded to the network interface between the channel subsystem and I/O device and specifies a location in the local memory of the ACW. On receipt of an I/O command message via the network a data transfer request from the network interface is issued and includes addressing information. A data route in the channel compares the ACW error checking field and the address control structure error checking field and if they match, the corresponding ACW is retrieved and used to route the data transfer request to the host memory (106) specified in the ACW.