公开(公告)号：PT90631A

公开(公告)日：1989-11-30

申请号：PT9063189

申请日：1989-05-23

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK E

IPC: G06F13/36 ,  G11C11/401 ,  G06F13/362 ,  G11C7/10 ,  G06F

Abstract: A computer system includes a page memory in which a row address accompanied by a row address strobe (RAS) is followed by a column address accompanied by a column address strobe (CAS) to read data from a memory location during a memory cycle. When, in a following memory cycle, a further location from the same page is to be accessed, the row address and the RAS remain constant and a new column address is used with the CAS being precharged by switching it to its OFF state and then returning it to its ON state. This is normally done at the start of the following memory cycle. In the present system, the data is read and latched shortly after arrival of the column address and CAS in the first of the memory cycles so that the CAS recharge can take place at the end of the first memory cycle and before the start of the following memory cycle.

公开(公告)号：PH30307A

公开(公告)日：1997-03-06

申请号：PH40475

申请日：1990-05-03

Applicant: IBM

Inventor： BEGUN RALPH M ,  DEAN MARK E ,  BLAND PATRICK M

IPC: G06F12/02 ,  G06F12/08

Abstract: The capacity of cache memory supported by a cache controller can be increased by offsetting the relationship between CPU address output terminals and address input terminals of the cache controller and correspondingly doubling the cache line size. In some cases, additional logic generates a hidden memory cycle so as to fetch from memory that number of bytes equal to the new line size regardless of the width of the data bus. The hidden memory cycle is initiated by a read miss and further logic generates a memory address which is not generated by the CPU. The hidden memory cycle is maintained transparent to the CPU and cache controller by inhibiting the change in a READY signal until completion of both the normal memory cycle and the hidden memory cycle.

公开(公告)号：PT90632B

公开(公告)日：1995-12-29

申请号：PT9063289

申请日：1989-05-23

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  BEGUN RALPH M ,  DEAN MARK E

IPC: G06F12/08

Abstract: A microcomputer system includes a microprocessor, a cache memroy, and a cache controller all coupled to a local bus. The local bus is coupled to a sytem bus, connecting the remaining system components, through latches. When writing data, the microcomputer can perform a posted write to a unit on the system bus by writing the data into the latches and then, on receipt of a ready signal from the cache controller, continuing its operations without waiting for the data to pas to its destination. A problem arises if the data is posted to a unit with a data width less than that of the microprocessor. In this case, the data should be sent in multiple cycles, but the read signal is generated before the data width of the unit is known and the microprocessor then continues its operations and can not, therefore, transmit the data correctly. To solve this problem, a logic unit is added to monitor the ready signal and the output of a decoder which detects non-cacheable addresses (which are of data width different from the microprocessor data width). If a non-cacheable address is detected, the read signal from the cache controller through the logic unit is withheld from the microprocessor, which now waits to continue processing beyond the write until a ready signal is received from the addressed unit on the system bus.

公开(公告)号：PT90631B

公开(公告)日：1994-10-31

申请号：PT9063189

申请日：1989-05-23

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK E

IPC: G06F13/36 ,  G11C11/401 ,  G06F13/362 ,  G11C7/10 ,  G11C7/00

Abstract: A computer system includes a page memory in which a row address accompanied by a row address strobe (RAS) is followed by a column address accompanied by a column address strobe (CAS) to read data from a memory location during a memory cycle. When, in a following memory cycle, a further location from the same page is to be accessed, the row address and the RAS remain constant and a new column address is used with the CAS being precharged by switching it to its OFF state and then returning it to its ON state. This is normally done at the start of the following memory cycle. In the present system, the data is read and latched shortly after arrival of the column address and CAS in the first of the memory cycles so that the CAS recharge can take place at the end of the first memory cycle and before the start of the following memory cycle.

公开(公告)号：CA1314330C

公开(公告)日：1993-03-09

申请号：CA597891

申请日：1989-04-26

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F12/08 ,  G06F13/20

Abstract: BC988-003 METHOD AND APPARATUS FOR SELECTIVELY POSTING WRITE CYCLES USING THE 82385 CACHE CONTROLLER A microcomputer system employing an 80386 CPU and an 82385 cache controller has the capability of functioning with dynamic bus sizing (where the CPU interacts with devices which may or may not be 32bits wide), as well as posted write capability. Unfortunately, the two capabilities have the possibility of an incompatibility if a write cycle is posted to a device which cannot transfer 32 bits on a single cycle. The present invention provides logic to overcome this incompatibility. An address decoder is provided to decode the tag portion or an address asserted on a CPU local bus to determine if the asserted address is inside or outside a range of addresses which define cacheable devices. Any cacheable device is by definition 32 bits wide and therefore posted writes are allowed only to cacheable devices. Accordingly, the microcomputer system employing the invention posts write cycles to cacheable devices; write cycles to non-cacheable devices are inhibited from being posted.

公开(公告)号：CA1314103C

公开(公告)日：1993-03-02

申请号：CA597892

申请日：1989-04-26

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F12/08 ,  G06F13/16 ,  G06F13/38

Abstract: BC388-G06 DELAYED CACHE WRITE ENABLE CIRCUIT FOR A DUAL BUS MICROCOMPUTER SYSTEM WITH AN 80386 AND 82385 In an 80386/82385 microcomputer system, the timing requirements placed on non-cache memory components by the 82385 are more stringent than the timing requirements placed on the non-cache memory components by the 80386. The present invention operates on the 82385 cache write enable (CWE) signals, and delays those signals in the event of a read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cacne memory components and at the same time does not impact wait state parameters for read miss operations.

公开(公告)号：AU627304B2

公开(公告)日：1992-08-20

申请号：AU5506090

申请日：1990-05-15

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F12/02 ,  G06F12/08

Abstract: The capacity of cache memory supported by a cache controller can be increased by offsetting the relationship between CPU address output terminals and address input terminals of the cache controller and correspondingly doubling the cache line size. In some cases, additional logic generates a hidden memory cycle so as to fetch from memory that number of bytes equal to the new line size regardless of the width of the data bus. The hidden memory cycle is initiated by a read miss and further logic generates a memory address which is not generated by the CPU. The hidden memory cycle is maintained transparent to the CPU and cache controller by inhibiting the change in a READY signal until completion of both the normal memory cycle and the hidden memory cycle.

公开(公告)号：DD295261A5

公开(公告)日：1991-10-24

申请号：DD34178290

申请日：1990-06-15

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F13/14

公开(公告)号：AU5506090A

公开(公告)日：1990-12-06

申请号：AU5506090

申请日：1990-05-15

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F12/02 ,  G06F12/08

Abstract: The capacity of cache memory supported by a cache controller can be increased by offsetting the relationship between CPU address output terminals and address input terminals of the cache controller and correspondingly doubling the cache line size. In some cases, additional logic generates a hidden memory cycle so as to fetch from memory that number of bytes equal to the new line size regardless of the width of the data bus. The hidden memory cycle is initiated by a read miss and further logic generates a memory address which is not generated by the CPU. The hidden memory cycle is maintained transparent to the CPU and cache controller by inhibiting the change in a READY signal until completion of both the normal memory cycle and the hidden memory cycle.

公开(公告)号：CA1216949A

公开(公告)日：1987-01-20

申请号：CA464459

申请日：1984-10-01

Applicant: IBM

Inventor： DEAN MARK E ,  MOELLER DENNIS L

IPC: G06F9/46 ,  G06F9/38 ,  G06F11/00 ,  G06F11/07 ,  G06F13/36 ,  G06F15/16 ,  G06F15/177

Abstract: DATA PROCESSING SYSTEM INCLUDING A MAIN PROCESSOR AND A CO-PROCESSOR AND CO-PROCESSOR ERROR HANDLING LOGIC In a data processing system including a main processor and a co-processor, a logic circuit is coupled to receive error and busy outputs of the co-processor to generate an interrupt output on co-incidence of active error and busy signals and to latch the busy signal to the main processor to ensure that the main processor will honor the interrupt before executing another co-processor instruction.