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公开(公告)号：CA2064162A1
公开(公告)日：1992-11-29
申请号：CA2064162
申请日：1992-03-26
Applicant: IBM
Inventor： FUOCO DANIEL P , HERNANDEZ LUIS A , MATHISEN ERIC , MOELLER DENNIS L , RAYMOND JONATHAN H , TASHAKORI ESMAEIL
IPC: G06F13/362 , G06F13/40 , G06F13/20
Abstract: This invention relates to personal computers, and more particularly to personal computers in which performance is enhanced by enabling arbitration for control over a local processor bus among a plurality of "master" devices coupled directly to the local processor bus. A personal computer system in accordance with this invention has a high speed local processor data bus; an input/output data bus; at least two master devices coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus, with the bus interface controller providing for arbitration among the master devices coupled directly to the local processor bus for access to the local processor bus, and providing for arbitration among the local processor bus and any devices coupled directly to the input/output data bus for access to the input/output data bus.
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公开(公告)号：BR9201917A
公开(公告)日：1993-01-12
申请号：BR9201917
申请日：1992-05-21
Applicant: IBM
Inventor： FUOCO DANIEL P , HERNANDEZ LUIS A , MATHISEN ERIC , MOELLER DENNIS L , RAYMOND JONATHAN H , TASHAKORI ESMAEIL
Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially requesting such access.
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公开(公告)号：CA1166754A
公开(公告)日：1984-05-01
申请号：CA399138
申请日：1982-03-23
Applicant: IBM
Inventor： MOELLER DENNIS L
Abstract: BC980020 BI-DIRECTIONAL SERIAL PRINTER WITH LOOK-AHEAD A bi-directional serial printer has a look-ahead feature which determines the distance between the margin of the line being printed and the margin, in the direction of the print head travel, of the next line to be printed. If this distance is less than a predetermined number, print head motion continues after printing the last character on the present line until the print head reaches the margin position for the next line.
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公开(公告)号：CA2064163C
公开(公告)日：1998-04-14
申请号：CA2064163
申请日：1992-03-26
Applicant: IBM
Inventor： FUOCO DANIEL P , RAYMOND JONATHAN H , MATHISEN ERIC , MOELLER DENNIS L , HERNANDEZ LUIS A , TASHAKORI ESMAEIL
Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially reqesting such access.
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公开(公告)号：BR9201915A
公开(公告)日：1993-01-12
申请号：BR9201915
申请日：1992-05-21
Applicant: IBM
Inventor： FUOCO DANIEL P , HERNANDEZ LUIS A , MATHISEN ERIC , MOELLER DENNIS L , RAYMOND JONATHAN HENRY , TASHAKORI ESMAEIL
Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for the usual system controlling processor to be reset, initialized and then isolated if an alternate system controller is provided for the system. In accordance with this invention, a personal computer system has a high speed local processor data bus; an input/output data bus; a microprocessor coupled directly to the local processor bus; a connector coupled directly to the local processor bus for accommodating reception of an alternate processor; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and the input/output data bus, with the bus interface controller providing for detection of the presence of an alternate processor received in the connector and, in response to detection of the presence of an alternate processor, transferring control of the local processor bus from the microprocessor to the alternate processor.
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Patent Agency Ranking
公开(公告)号：CA2064163A1
公开(公告)日：1992-11-29
申请号：CA2064163
申请日：1992-03-26
Applicant: IBM
Inventor： FUOCO DANIEL P , HERNANDEZ LUIS A , MATHISEN ERIC , MOELLER DENNIS L , RAYMOND JONATHAN H , TASHAKORI ESMAEIL
Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially requesting such access.
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公开(公告)号：CA1293816C
公开(公告)日：1991-12-31
申请号：CA565618
申请日：1988-04-29
Applicant: IBM
Inventor： LO YUAN-CHANG , MOELLER DENNIS L , SZAREK JOHN J
Abstract: BC9-86-008 MEMORY RE-MAPPING IN A MICROCOMPUTER SYSTEM A microcomputer system has first, low order address, memory means soldered to the planar printed circuit board and can accept further memory means pluggable into socket means on the board. At power on self test, the memory means are tested, and, if an error is detected in the first memory means, this memory means is disabled by directing the lowest order memory addresses to the second memory means and reducing the highest order addresses by the number of locations in the first memory means.
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公开(公告)号：CA2099026A1
公开(公告)日：1994-03-18
申请号：CA2099026
申请日：1993-06-23
Applicant: IBM
Inventor： BLACKLEDGE JOHN W JR , DAYAN RICHARD A , MOELLER DENNIS L , NEWMAN PALMER E , ZUBAY KENNETH J P
Abstract: This invention relates to personal computer systems and, more particularly, to such a system having security features enabling control over access to data retained in such a system. This invention contemplates protecting a personal computer system which has the capability of becoming a secure system from being placed into that condition by an attack on an unsecured machine. Additionally, in a network environment, it is important to maintain network security that any given particular system be uniquely identified to the network, in order to guard against the substitution of an insecure "alternate" which would open the network to attack through an insecure system. This invention contemplates provision for such identification in a secure manner.
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公开(公告)号：CA2082916A1
公开(公告)日：1993-08-27
申请号：CA2082916
申请日：1992-11-13
Applicant: IBM
Inventor： BLACKLEDGE JOHN W JR , CLARKE GRANT L JR , DAYAN RICHARD A , LE KIMTHANH D , MCCOURT PATRICK E , MITTELSTEDT MATHEW T , MOELLER DENNIS L , NEWMAN PALMER E , RANDALL DAVE L , YODER JOANNA B
Abstract: This invention relates to personal computer systems and, more particularly, to such a system having security features enabling control over access to data retained in such a system. In particular, a personal computer system in accordance with this invention has a normally closed enclosure, an erasable memory element for selective activation to active and inactive states and for receiving and storing a privileged access password when in the active state, an option switch operatively connected with the erasable memory element for setting the erasable memory element to the active and inactive states, a tamper detection switch operatively connected with the erasable memory element for detecting opening of the enclosure and for clearing any stored privileged access password from the erasable memory element in response to any switching of the tamper switch, and a system processor operatively connected with the erasable memory element for controlling access to at least certain levels of data stored within the system by distinguishing between the active and inactive states of the memory element and between entry and non-entry of any stored privileged access password. In the presently preferred form of the invention, two non-volatile erasable memory elements are provided, one an EEPROM and the other battery backed CMOS RAM.
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公开(公告)号：CA2065997A1
公开(公告)日：1992-11-29
申请号：CA2065997
申请日：1992-04-14
Applicant: IBM
Inventor： FUOCO DANIEL P , HERNANDEZ LUIS A , MATHISEN ERIC , MOELLER DENNIS L , RAYMOND JONATHAN H , TASHAKORI ESMAEIL
Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for the usual system controlling processor to be reset, initialized and then isolated if an alternate system controller is provided for the system. In accordance with this invention, a personal computer system has a high speed local processor data bus; an input/output data bus; a microprocessor coupled directly to the local processor bus; a connector coupled directly to the local processor bus for accommodating reception of an alternate processor; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and the input/output data bus, with the bus interface controller providing for detection of the presence of an alternate processor received in the connector and, in response to detection of the presence of an alternate processor, transferring control of the local processor bus from the microprocessor to the alternate processor.
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