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公开(公告)号：RU2213992C2
公开(公告)日：2003-10-10
申请号：RU2001126557
申请日：2000-03-03
Applicant: IBM
Inventor： DREPS DANIEL MARK , FERRAJOLO FRANK DEJVID , GAUEHR KEVIN CHARLZ
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公开(公告)号：CZ20013179A3
公开(公告)日：2002-02-13
申请号：CZ20013179
申请日：2000-03-03
Applicant: IBM
Inventor： DREPS DANIEL MARK , FERRAIOLO FRANK DAVID , GOWER KEVIN CHARLES
Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.
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公开(公告)号：GB2318936A
公开(公告)日：1998-05-06
申请号：GB9720705
申请日：1997-09-30
Applicant: IBM
Inventor： DREPS DANIEL MARK , MASLEID ROBERT P , MUHICH JOHN S
Abstract: A clock generation apparatus and method for generating clock signals for a microprocessor integrated circuit which includes a device which generates a reference frequency 26, an acoustic wave oscillator 18 having an oscillation frequency slightly faster than the reference frequency 26 and a circuit configuration coupled to the acoustic wave oscillator which generates frequency signals in response to an output of the acoustic wave oscillator. The frequency signals carry negligible jitter. The circuit configuration includes a quadrature rotator 12 for controlling clock phase, a clock distributor 14 for efficiently dispersing clock signals to the microprocessor integrated circuit, a bus divider 24 which provides a feedback clock signal phase aligned with the reference frequency, a phase detector 22 for detecting the phase difference of a bus clock signal and the feedback clock signal, and a digital filter 20 responsive to the phase detector.
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公开(公告)号：CA2366898C
公开(公告)日：2005-04-12
申请号：CA2366898
申请日：2000-03-03
Applicant: IBM
Inventor： DREPS DANIEL MARK , FERRAIOLO FRANK DAVID , GOWER KEVIN CHARLES
Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage i n the corresponding storage unit. Data is sequentially output from each storag e unit in synchrony with the local clock on a target cycle of the local clock.
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公开(公告)号：ES2193940T3
公开(公告)日：2003-11-16
申请号：ES00907773
申请日：2000-03-03
Applicant: IBM
Inventor： DREPS DANIEL MARK , FERRAIOLO FRANK DAVID , GOWER KEVIN CHARLES
Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.
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Patent Agency Ranking
公开(公告)号：AT239944T
公开(公告)日：2003-05-15
申请号：AT00907775
申请日：2000-03-03
Applicant: IBM
Inventor： DREPS DANIEL MARK , FERRAIOLO FRANK DAVID , GOWER KEVIN CHARLES
Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.
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公开(公告)号：PL350160A1
公开(公告)日：2002-11-18
申请号：PL35016000
申请日：2000-03-03
Applicant: IBM
Inventor： DREPS DANIEL MARK , FERRAIOLO FRANK DAVID , GOWER KEVIN CHARLES
Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.
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公开(公告)号：DE19852457C2
公开(公告)日：2002-07-11
申请号：DE19852457
申请日：1998-11-13
Applicant: IBM
Inventor： DREPS DANIEL MARK , MASLEID ROBERT PAUL , MUHICH JOHN STEPHEN
IPC: G06F1/06 , G06F1/04 , G06F1/10 , H03K5/135 , H03L7/06 , H03L7/081 , H03L7/099 , H03K5/153 , H03L7/089
Abstract: Among a plurality of signals, each phase-shifted with respect to the others, one signal is repeatedly substituted for another as a clock signal, to reduce a phase error of the clock signal with respect to a reference clock. The substitutions are timed to occur during intervals tending to reduce disturbances to the clock signal. Also, such substitution of a signal is responsive to occurrence of at least one cycle of the signal subsequent to the clock being supplied by an immediate predecessor of the signal, which tends to prevent erroneous substitutions of one signal for another.
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公开(公告)号：HU0200283A2
公开(公告)日：2002-05-29
申请号：HU0200283
申请日：2000-03-03
Applicant: IBM
Inventor： DREPS DANIEL MARK , FERRAIOLO FRANK DAVID , GOWER KEVIN CHARLES
Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.
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公开(公告)号：GB2318936B
公开(公告)日：2001-01-17
申请号：GB9720705
申请日：1997-09-30
Applicant: IBM
Inventor： DREPS DANIEL MARK , MASLEID ROBERT P , MUHICH JOHN S
Abstract: A clock generation apparatus and method for generating clock signals for a microprocessor integrated circuit. The clock generation apparatus includes a device which generates a reference frequency, an acoustic wave oscillator having an oscillation frequency slightly faster than the reference frequency and a circuit configuration coupled to the acoustic wave oscillator which generates frequency bearing signals in response to an output of the acoustic wave oscillator. The frequency bearing signals carry negligible jitter. The circuit configuration includes a quadrature rotator for controlling clock phase, a clock distributor for efficiently dispersing clock signals to the microprocessor integrated circuit, a bus divider which provides a feedback clock signal phase aligned with the reference frequency, a phase detector for detecting the phase difference of a bus clock signal and the feedback clock signal, and a digital filter responsive to the phase detector.
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