公开(公告)号：JPH11259167A

公开(公告)日：1999-09-24

申请号：JP4999

申请日：1999-01-04

Applicant: IBM

Inventor： DREPS DANIEL MARK ,  MASLEID ROBERT PAUL ,  MUHICH JOHN STEPHEN

IPC: G06F1/04 ,  G06F1/10 ,  H03L7/00 ,  H03L7/07 ,  H04L7/02

Abstract: PROBLEM TO BE SOLVED: To provide a clock generating device useful for a high-speed subminiature electronic device by making a 1st series of signals succeeding to one another in response to a 1st phase difference, a 2nd series of signals succeed to one another in response to a 2nd phase difference, and the 1st series of signals respond to the 2nd phase difference. SOLUTION: In response to a reference signal from a SAW generator 104, a 1st DLL digital locked loop rotating means 118 generates 1st signals and in response to a reference signal from a SAW transmitter 104, a 2nd DLL rotating means 116 generates 2nd signals respectively. A clock frequency divider 130 divides the frequency of a 1st clock signal by a multiple of 2 with the 1st series of signals and supplies the result to an off-chip memory 108. With the 2nd series of signals, a 2nd clock signal is supplied to a clock distribution system 128. Those series of signals are made to succeed to one another in response to the phase differences of phase detectors 132 and 134.

公开(公告)号：JPH11316616A

公开(公告)日：1999-11-16

申请号：JP5099

申请日：1999-01-04

Applicant: IBM

Inventor： DREPS DANIEL MARK ,  MASLEID ROBERT PAUL ,  MUHICH JOHN STEPHEN

IPC: G06F1/06 ,  G06F1/04 ,  G06F1/10 ,  H03K5/135 ,  H03L7/06 ,  H03L7/081 ,  H03L7/099

Abstract: PROBLEM TO BE SOLVED: To reduce the phase difference between clock signals and also to reduce the disturbance in clock signals caused by substitution by substituting a selected 1st clock signal for a 2nd signal among plural signals whose phases are shifted to the 1st clock signal for reduction of the phase difference between the 1st clock signal and a reference clock signal. SOLUTION: A 1st clock signal is selected out of four internal source signals of a rotation means 14 and outputted. A phase detector 20 compares a reference clock signal 21 with the 1st clock signal and generates an output signal to show the phase difference between the signal 21 and the 1st clock signal. Then the output signal is fed back to the means 14 through a digital filter 22. The means 14 delays the source to be selected for the 1st clock signal by changing continuously one of plural source signals that is kept in a halt state to another. Then the means 14 locks the phase of a feedback clock signal against the signal 21.

公开(公告)号：AU6855790A

公开(公告)日：1991-08-01

申请号：AU6855790

申请日：1990-12-28

Applicant: IBM

Inventor： MASLEID ROBERT PAUL ,  PATEL PARSOTAM TRIKAM

IPC: H01L21/822 ,  G06F17/50 ,  H01L21/82 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/04 ,  H01L27/092 ,  H01L27/118 ,  H01L27/10

Abstract: In accordance with the teachings of this invention a method for positioning components of input/output circuits is provided. These components are positioned on a semiconductor substrate. The semiconductor substrate includes other than input/output circuits. Each input/output circuit is provided for processing a single bit of information within a data word containing multiple bits. The method includes the step of (1) dividing each input/output circuit into groups containing similar functional subcomponents; (2) forming a vertical column of subcomponents for each input/output circuit and connecting these subcomponents to perform the function; (3) placing said columns in adjacency to form a plurality of columns with like subcomponents immediately adjacent to each other forming row groups of said like subcomponents; and (4) forming guard rings around the subcomponent row groups if required. Also in accordance with this invention, a group of input/output circuits is provided. The group is positioned on an integrated circuit substrate that contains other than input/output circuits. The input/output circuits group includes a plurality of columns of circuitry component where each column represents all of the input/output circuit components for processing a single bit of information in a group of bits, a plurality of rows positioned across the columns containing like devices among said input/output circuits, and at least one guard ring containing at least one of the plurality of rows.

公开(公告)号：DE3773582D1

公开(公告)日：1991-11-14

申请号：DE3773582

申请日：1987-07-21

Applicant: IBM

Inventor： MASLEID ROBERT PAUL ,  SCHMOOKLER MARTIN STANLEY

IPC: H03K19/017 ,  H03K19/177

Abstract: A programmable logic array comprises: a plurality of electrically isolated input lines (eg 204, 206, 208, 210); input means (200) for addressing the plurality of input lines and directing an input signal to an addressed one thereof; a plurality of electrically isolated output lines (220, 228) positioned to form a plurality of nonconductive intersections with said input lines; an individual transistor (212, 214, 216, 218, 230, 232, 234, 236) disposed at each intersection, the control electrode of the transistor being connected to one of the input lines and one current flow electrode of the transistor being connected to one of the output lines and the other current flow electrode of the transistor being connected to a selected one of two potential sources (GND, +V), the selection being made in the course of programming the array, whereby a programmed output signal is obtained on the output line to which said one currant flow electrode is connected when an input signal is directed to an addressed input line.

公开(公告)号：DE19852457A1

公开(公告)日：1999-07-08

申请号：DE19852457

申请日：1998-11-13

Applicant: IBM

Inventor： DREPS DANIEL MARK ,  MASLEID ROBERT PAUL ,  MUHICH JOHN STEPHEN

IPC: G06F1/06 ,  G06F1/04 ,  G06F1/10 ,  H03K5/135 ,  H03L7/06 ,  H03L7/081 ,  H03L7/099 ,  H03K5/153 ,  H03L7/089

Abstract: A clock generating system has a phase detector (20) that compares a reference clock signal (21) with a feedback clock signal from a frequency divider (18) coupled to the load system (16). The phase difference signal and feedback signals are fed through a digital filter (22) as input to a phase shifting stage (14) to apply a correction.

公开(公告)号：DE19852457C2

公开(公告)日：2002-07-11

申请号：DE19852457

申请日：1998-11-13

Applicant: IBM

Inventor： DREPS DANIEL MARK ,  MASLEID ROBERT PAUL ,  MUHICH JOHN STEPHEN

IPC: G06F1/06 ,  G06F1/04 ,  G06F1/10 ,  H03K5/135 ,  H03L7/06 ,  H03L7/081 ,  H03L7/099 ,  H03K5/153 ,  H03L7/089

Abstract: Among a plurality of signals, each phase-shifted with respect to the others, one signal is repeatedly substituted for another as a clock signal, to reduce a phase error of the clock signal with respect to a reference clock. The substitutions are timed to occur during intervals tending to reduce disturbances to the clock signal. Also, such substitution of a signal is responsive to occurrence of at least one cycle of the signal subsequent to the clock being supplied by an immediate predecessor of the signal, which tends to prevent erroneous substitutions of one signal for another.

公开(公告)号：DE69128434D1

公开(公告)日：1998-01-29

申请号：DE69128434

申请日：1991-01-04

Applicant: IBM

Inventor： MASLEID ROBERT PAUL ,  PATEL PARSOTAM TRIKAM

IPC: G06F17/50 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/04 ,  H01L27/092 ,  H01L27/118 ,  H01L27/02

Abstract: In accordance with the teachings of this invention a method for positioning components of input/output circuits is provided. These components are positioned on a semiconductor substrate. The semiconductor substrate includes other than input/output circuits. Each input/output circuit is provided for processing a single bit of information within a data word containing multiple bits. The method includes the step of (1) dividing each input/output circuit into groups containing similar functional subcomponents; (2) forming a vertical column of subcomponents for each input/output circuit and connecting these subcomponents to perform the function; (3) placing said columns in adjacency to form a plurality of columns with like subcomponents immediately adjacent to each other forming row groups of said like subcomponents; and (4) forming guard rings around the subcomponent row groups if required. Also in accordance with this invention, a group of input/output circuits is provided. The group is positioned on an integrated circuit substrate that contains other than input/output circuits. The input/output circuits group includes a plurality of columns of circuitry component where each column represents all of the input/output circuit components for processing a single bit of information in a group of bits, a plurality of rows positioned across the columns containing like devices among said input/output circuits, and at least one guard ring containing at least one of the plurality of rows.

公开(公告)号：SG44408A1

公开(公告)日：1997-12-19

申请号：SG1996000215

申请日：1991-01-04

Applicant: IBM

Inventor： MASLEID ROBERT PAUL ,  PATEL PARSOTAM TRIKAM

IPC: G06F17/50 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/04 ,  H01L27/092 ,  H01L27/118 ,  H01L27/02

Abstract: In accordance with the teachings of this invention a method for positioning components of input/output circuits is provided. These components are positioned on a semiconductor substrate. The semiconductor substrate includes other than input/output circuits. Each input/output circuit is provided for processing a single bit of information within a data word containing multiple bits. The method includes the step of (1) dividing each input/output circuit into groups containing similar functional subcomponents; (2) forming a vertical column of subcomponents for each input/output circuit and connecting these subcomponents to perform the function; (3) placing said columns in adjacency to form a plurality of columns with like subcomponents immediately adjacent to each other forming row groups of said like subcomponents; and (4) forming guard rings around the subcomponent row groups if required. Also in accordance with this invention, a group of input/output circuits is provided. The group is positioned on an integrated circuit substrate that contains other than input/output circuits. The input/output circuits group includes a plurality of columns of circuitry component where each column represents all of the input/output circuit components for processing a single bit of information in a group of bits, a plurality of rows positioned across the columns containing like devices among said input/output circuits, and at least one guard ring containing at least one of the plurality of rows.