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公开(公告)号：JPH10320198A
公开(公告)日：1998-12-04
申请号：JP9133098
申请日：1998-04-03
Applicant: IBM
Inventor： FEISTE KURT ALAN , MUHICH JOHN STEPHEN , THATCHER LARRY EDWARD , WHITE STEVEN WAYNE
Abstract: PROBLEM TO BE SOLVED: To transfer stored data to a necessary load instruction without stalling the long instruction until storage completion by transferring store data to the load instruction when a store instruction is already converted, a load address range is included in a store address range, and the store data are usable. SOLUTION: This is a method for transferring data as the result of a store instruction which does not have updated data to the load instruction and a CPU 120 judges whether or not there is a common byte between the address of the load instruction and the address of the store instruction. Further, it is judged whether or not the load instruction is logically behind the store instruction. When there is the common byte between the address of the load instruction and the address of the store instruction and when the load instruction is logically behind the store instruction, the data is transferred to the load instruction.
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公开(公告)号：JPH11259167A
公开(公告)日：1999-09-24
申请号：JP4999
申请日：1999-01-04
Applicant: IBM
Inventor： DREPS DANIEL MARK , MASLEID ROBERT PAUL , MUHICH JOHN STEPHEN
Abstract: PROBLEM TO BE SOLVED: To provide a clock generating device useful for a high-speed subminiature electronic device by making a 1st series of signals succeeding to one another in response to a 1st phase difference, a 2nd series of signals succeed to one another in response to a 2nd phase difference, and the 1st series of signals respond to the 2nd phase difference. SOLUTION: In response to a reference signal from a SAW generator 104, a 1st DLL digital locked loop rotating means 118 generates 1st signals and in response to a reference signal from a SAW transmitter 104, a 2nd DLL rotating means 116 generates 2nd signals respectively. A clock frequency divider 130 divides the frequency of a 1st clock signal by a multiple of 2 with the 1st series of signals and supplies the result to an off-chip memory 108. With the 2nd series of signals, a 2nd clock signal is supplied to a clock distribution system 128. Those series of signals are made to succeed to one another in response to the phase differences of phase detectors 132 and 134.
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公开(公告)号：JPH11316616A
公开(公告)日：1999-11-16
申请号：JP5099
申请日：1999-01-04
Applicant: IBM
Inventor： DREPS DANIEL MARK , MASLEID ROBERT PAUL , MUHICH JOHN STEPHEN
Abstract: PROBLEM TO BE SOLVED: To reduce the phase difference between clock signals and also to reduce the disturbance in clock signals caused by substitution by substituting a selected 1st clock signal for a 2nd signal among plural signals whose phases are shifted to the 1st clock signal for reduction of the phase difference between the 1st clock signal and a reference clock signal. SOLUTION: A 1st clock signal is selected out of four internal source signals of a rotation means 14 and outputted. A phase detector 20 compares a reference clock signal 21 with the 1st clock signal and generates an output signal to show the phase difference between the signal 21 and the 1st clock signal. Then the output signal is fed back to the means 14 through a digital filter 22. The means 14 delays the source to be selected for the 1st clock signal by changing continuously one of plural source signals that is kept in a halt state to another. Then the means 14 locks the phase of a feedback clock signal against the signal 21.
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公开(公告)号：HK139594A
公开(公告)日：1994-12-16
申请号：HK139594
申请日：1994-12-08
Applicant: IBM
Inventor： KAUFFMAN ARTHUR AMOS , MUHICH JOHN STEPHEN
IPC: G06F12/02 , G06F3/14 , G06F3/153 , G06F12/00 , G06T1/00 , G06T1/60 , G06T3/60 , G11C7/00 , G11C11/401 , G06F15/62
Abstract: A data display system having a memory circuit including a bit addressable binary data memory in which the data is stored in a plurality of dimensional directions and a circuit for accessing a group of the data in the memory in at least two of the dimensional directions and for moving the data to a different dimensional location while maintaining the data within the group. Also provided is a means for accessing the data by incrementally or decrementally addressing the data in at least one of the directions. The accessing circuitry is further used to perform bit block transfers of data within the memory. The accessing circuit also provides for horizontal or vertical access during a read operation while orthogonally rotating the data by 90 degrees during a following write operation.
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公开(公告)号：DE19852457A1
公开(公告)日：1999-07-08
申请号：DE19852457
申请日：1998-11-13
Applicant: IBM
Inventor： DREPS DANIEL MARK , MASLEID ROBERT PAUL , MUHICH JOHN STEPHEN
IPC: G06F1/06 , G06F1/04 , G06F1/10 , H03K5/135 , H03L7/06 , H03L7/081 , H03L7/099 , H03K5/153 , H03L7/089
Abstract: A clock generating system has a phase detector (20) that compares a reference clock signal (21) with a feedback clock signal from a frequency divider (18) coupled to the load system (16). The phase difference signal and feedback signals are fed through a digital filter (22) as input to a phase shifting stage (14) to apply a correction.
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Patent Agency Ranking
公开(公告)号：DE3688513T2
公开(公告)日：1993-12-23
申请号：DE3688513
申请日：1986-01-02
Applicant: IBM
Inventor： BAKER DAVID CURETON , MUHICH JOHN STEPHEN
Abstract: ® A memory array (16) associated with a display (22) can be accessed in either one of two substantially orthogonal directions. The memory array is structured so that it may be accessed, such as for reading or writing, in either the hor- lzontal or vertical direction. Pei position representations in the array are arranged so that vertically sequential pel positions in a given column are represented by data in sequential memory modules rather than by data in the same memory module. Likewise, horizontally sequential pels in a given row are represented by data in sequential modules rather than in the same module. The memory array is comprised of a plurality of separate memory modules and is structured so that both x and y directional accessing into and out of the array is accomplished on a bit addressable x, y field. This enables any bit string in the array to be addressed and to be read from or written into the array in either the x or y direction. No word or byte boundaries exist in either the x direction of access or the y direction of access.
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公开(公告)号：DE3688513D1
公开(公告)日：1993-07-08
申请号：DE3688513
申请日：1986-01-02
Applicant: IBM
Inventor： BAKER DAVID CURETON , MUHICH JOHN STEPHEN
Abstract: ® A memory array (16) associated with a display (22) can be accessed in either one of two substantially orthogonal directions. The memory array is structured so that it may be accessed, such as for reading or writing, in either the hor- lzontal or vertical direction. Pei position representations in the array are arranged so that vertically sequential pel positions in a given column are represented by data in sequential memory modules rather than by data in the same memory module. Likewise, horizontally sequential pels in a given row are represented by data in sequential modules rather than in the same module. The memory array is comprised of a plurality of separate memory modules and is structured so that both x and y directional accessing into and out of the array is accomplished on a bit addressable x, y field. This enables any bit string in the array to be addressed and to be read from or written into the array in either the x or y direction. No word or byte boundaries exist in either the x direction of access or the y direction of access.
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公开(公告)号：AT242509T
公开(公告)日：2003-06-15
申请号：AT98301659
申请日：1998-03-06
Applicant: IBM
Inventor： FEISTE KURT ALAN , MUHICH JOHN STEPHEN , THATCHER LARRY EDWARD , WHITE STEVEN WAYNE
Abstract: In a superscalar processor implementing out-of-order dispatching and execution of load and store instructions, when a store instruction has already been translated, the load address range of a load instruction is contained within the address range of the store instruction, and the data associated with the store instruction is available, then the data associated with the store instruction is forwarded to the load instruction so that the load instruction may continue execution without having to be stalled or flushed.
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公开(公告)号：DE69327288D1
公开(公告)日：2000-01-20
申请号：DE69327288
申请日：1993-09-20
Applicant: IBM
Inventor： MOORE CHARLES ROBERTS , MUHICH JOHN STEPHEN
IPC: G06F12/08 , G06F12/10 , G06F15/16 , G06F15/177
Abstract: Translation lookaside buffers (TLB) are often utilized in the data processing system to efficiently translate an effective or virtual address to a real address within system memory. In systems which include multiple processors which may all access system memory, each processor may include a translation lookaside buffer (TLB) for translating effective addresses to real addresses and coherency between all translation lookaside buffers (TLB) must therefore be maintained. The method and system disclosed herein may be utilized to broadcast a unique bus structure in response to an execution of a translation lookaside buffer invalidate (TLBI) instruction by any processor within a multiprocessor system. The bus structure is accepted by other processors along the bus only in response to an absence of a pending translation lookaside buffer invalidate (TLBI) instruction within each processor. Thus, a broadcast translation lookaside buffer invalidate (TLBI) instruction may only be executed by the other processors within a multiprocessor system if it has been accepted by all processors within the system. After initiating execution of a translation lookaside buffer invalidate (TLBI) instruction at all processors within the system, the execution of pending instructions is temporarily terminated until after the translation lookaside buffer invalidate (TLBI) instruction has been executed. Thereafter, the execution of instructions is suspended until all read and write operations within the memory queue have achieved coherency. Next, all suspended and/or prefetched instructions are refetched utilizing the modified translation lookaside buffer (TLB) to ensure that the address utilized is still valid.
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