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公开(公告)号：CA2385339C
公开(公告)日：2005-06-28
申请号：CA2385339
申请日：2000-12-21
Applicant: IBM
Inventor： JENKINS STEVEN KENNETH , SIEGEL MICHAEL STEVEN , CALVIGNAC JEAN LOUIS , BASS BRIAN MITCHELL , LEAVENS ROSS BOYD , VERPLANKEN FABRICE JEAN , HEDDES MARCO , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristic s for the frame (or input information unit) include the type of layer 3 protoc ol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics o f the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction addre ss and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed a nd forwarded in the same order in which they are received.
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公开(公告)号：AU4441801A
公开(公告)日：2001-10-23
申请号：AU4441801
申请日：2001-04-10
Applicant: IBM
Inventor： GALLO ANTHONY MATTEO , HEDDES MARCO , HARIHARAN SEETA , RAO SRIDHAR , ROVER SONIA KIANG
Abstract: A system and method for controlling overall behavior of a network processor device implemented in a network processing environment servicing a communications network. The method includes steps of receiving a guided control frame including one or more control functions for configuring various functional devices within the network processor with device control parameter data; a step of forwarding one or more control functions from a received control frame to a functional device within the network processor to be configured; and, executing the control functions as specified in the control frame. A novel control frame data structure and communications infrastructure is implemented whereby any network processor device operating in a distributed network processing environment may be controlled in accordance with executed control functions and device control parameter data.
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公开(公告)号：CA2385339A1
公开(公告)日：2001-07-12
申请号：CA2385339
申请日：2000-12-21
Applicant: IBM
Inventor： HEDDES MARCO , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , GALLO ANTHONY MATTEO , DAVIS GORDON TAYLOR , BASS BRIAN MITCHELL , VERPLANKEN FABRICE JEAN , CALVIGNAC JEAN LOUIS , JENKINS STEVEN KENNETH
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristic s for the frame (or input information unit) include the type of layer 3 protoc ol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics o f the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction addre ss and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed a nd forwarded in the same order in which they are received.
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公开(公告)号：ES2265971T3
公开(公告)日：2007-03-01
申请号：ES00959158
申请日：2000-08-24
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , GALLO ANTHONY MATTEO , HEDDES MARCO C , RAO SRIDHAR , SIEGEL MICHAEL STEVEN
IPC: G06F13/00 , G06F15/16 , G06F13/38 , G06F13/40 , G06F15/00 , G06F15/173 , G06F15/177 , G06F15/76 , H04L12/56
Abstract: Aparato que comprende: un procesador del punto de control; un dispositivo de interfaz conectado operativamente a dicho procesador del punto de control por un camino de control y que proporciona un camino de datos de alta velocidad, teniendo dicho dispositivo de interfaz un substrato (10) de semiconductores; una pluralidad de procesadores (12) del interfaz formados sobre dicho substrato, siendo el número de dichos procesadores al menos cinco; una memoria interna de instrucciones formada sobre dicho substrato y que almacena instrucciones de manera accesible para dichos procesadores del interfaz; una memoria interna de datos formada sobre dicho substrato y que almacena datos que pasan a través de dicho dispositivo, de manera accesible para dichos procesadores del interfaz; y una pluralidad de puertos de entrada/salida formados sobre dicho substrato; conectando al menos uno de dichos puertos de entrada/salida a dicha memoria interna de datos con la memoria externa de datos; intercambiando, al menos otros dos de dichos puertos de entrada/salida, datos que pasan a través del dispositivo de interfaz, con una red externa a la velocidad del medio bajo la dirección de dichos procesadores del interfaz; cooperando dicho procesador del punto de control con dicho dispositivo de interfaz, cargando en el interior de dicha memoria de instrucciones las instrucciones que han de ser ejecutadas por dichos procesadores del interfaz al dirigir el intercambio de datos entre dichos puertos de entrada/salida de intercambio de datos y el flujo de datos a través de dicha memoria de datos.
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公开(公告)号：PL355786A1
公开(公告)日：2004-05-17
申请号：PL35578600
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVID GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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Patent Agency Ranking
公开(公告)号：HK1054098A1
公开(公告)日：2003-11-14
申请号：HK03106314
申请日：2003-09-05
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , MARCO HEDDES , KENNETH JENKINS STEVEN , BOYD LEAVENS ROSS , STEVEN SIEGEL MICHAEL , JEAN VERPLANKEN FABRICE
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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公开(公告)号：CZ20021442A3
公开(公告)日：2002-07-17
申请号：CZ20021442
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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公开(公告)号：PL356725A1
公开(公告)日：2004-06-28
申请号：PL35672500
申请日：2000-11-21
Applicant: IBM
Inventor： AYDEMIR METIN , BASS BRIAN MITCHELL , JEFFRIES CLARK DEBS , ROVNER SONIA KIANG , SIEGEL MICHAEL STEVEN , GALLO ANTHONY MATTEO , GORTI BRAHMANAND KUMAR , HEDDES MARCO
Abstract: Methods, apparatus and program products for controlling a flow of a plurality of packets in a computer network are disclosed. The computer network includes a device defining a queue. The methods, apparatus and program products include determining a queue level for the queue and determining an offered rate of the plurality of packets to the queue. They also include controlling a transmission fraction of the plurality of packets to or from the queue, based on the queue level, the offered rate and a previous value of the transmission fraction so that the transmission fraction and the queue level are critically damped if the queue level is between at least a first queue level and a second queue level. Several embodiments are disclosed in which various techniques are used to determine the manner of the control.
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公开(公告)号：HU0203823A2
公开(公告)日：2003-05-28
申请号：HU0203823
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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公开(公告)号：BR0015717A
公开(公告)日：2002-07-23
申请号：BR0015717
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINSS STEVEN KENNETH , LEAVENS ROSS BODY , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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