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公开(公告)号：JP2001222465A
公开(公告)日：2001-08-17
申请号：JP2000390789
申请日：2000-12-22
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , HEDDES MARCO C , JENKINS STEVEN KENNETH , SIEGEL MICHAEL STEVEN , MICHAEL RAYMOND TROMBLAY , VERPLANKEN FABRICE JEAN
IPC: G06F12/06 , G06F12/00 , G06F12/02 , G06F13/00 , G06F13/16 , G06F15/167 , G11C11/407 , H04L12/56
Abstract: PROBLEM TO BE SOLVED: To improve the capacity of a network processor for moving data to a dynamic random access memory(DRAM) chip to be used for a computer system or moving data from the chip. SOLUTION: Two double data rate DRAMs are used in order to double band width in accordance with the throughput of increased data. The movement of data is further improved by setting up complete reading of four banks and complete writing of four banks by a network processor in each repeat of a DRAM time clock. A scheme for reading and writing accesses randomized by the network processor is discloses. The scheme can be applied especially to a network such as the Ethernet (R) using various frame sizes.
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公开(公告)号：ES2226958T3
公开(公告)日：2005-04-01
申请号：ES00983409
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH
Abstract: Un aparato que comprende: un substrato semiconductor; N unidades (110) de procesamiento fabricadas sobre el substrato, donde N > 1; una primera memoria de datos interna accesible para dichas N unidades de procesamiento; una unidad (112) de expedición acoplada operativamente a las N unidades de procesamiento para recibir y transmitir una unidad de información de entrada a una de las N unidades de procesamiento; una unidad (118) de clasificación acoplada a la unidad (112) de expedición, incluyendo dicha unidad de clasificación una unidad (114) de comparación para determinar un formato de datos para una unidad de información de entrada y para generar y almacenar en la memoria de datos interna indicadores de salida para la unidad de información de entrada, que indican el formato de datos de la unidad de información de entrada y una dirección de arranque para la unidad de información de entrada, cuyos indicadores y dirección de arranque están disponibles para una de las N unidades de procesamiento durante su procesamiento de la unidad de información de entrada y son utilizados en el procesamiento de la unidad de información de entrada; y una unidad (114) de compleción soportada en el substrato semiconductor y conectada operativamente a las N unidades (110) de procesamiento para recibir la unidad de información procesada por la unidad considerada de las N unidades (110) de procesamiento.
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公开(公告)号：CA2385339C
公开(公告)日：2005-06-28
申请号：CA2385339
申请日：2000-12-21
Applicant: IBM
Inventor： JENKINS STEVEN KENNETH , SIEGEL MICHAEL STEVEN , CALVIGNAC JEAN LOUIS , BASS BRIAN MITCHELL , LEAVENS ROSS BOYD , VERPLANKEN FABRICE JEAN , HEDDES MARCO , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristic s for the frame (or input information unit) include the type of layer 3 protoc ol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics o f the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction addre ss and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed a nd forwarded in the same order in which they are received.
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公开(公告)号：CA2385339A1
公开(公告)日：2001-07-12
申请号：CA2385339
申请日：2000-12-21
Applicant: IBM
Inventor： HEDDES MARCO , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , GALLO ANTHONY MATTEO , DAVIS GORDON TAYLOR , BASS BRIAN MITCHELL , VERPLANKEN FABRICE JEAN , CALVIGNAC JEAN LOUIS , JENKINS STEVEN KENNETH
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristic s for the frame (or input information unit) include the type of layer 3 protoc ol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics o f the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction addre ss and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed a nd forwarded in the same order in which they are received.
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公开(公告)号：AT280411T
公开(公告)日：2004-11-15
申请号：AT00983409
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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Patent Agency Ranking
公开(公告)号：AU2016601A
公开(公告)日：2001-07-16
申请号：AU2016601
申请日：2000-12-21
Applicant: IBM
Inventor： CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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公开(公告)号：HU0203823A2
公开(公告)日：2003-05-28
申请号：HU0203823
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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公开(公告)号：CA2316122A1
公开(公告)日：2001-07-04
申请号：CA2316122
申请日：2000-08-17
Applicant: IBM
Inventor： CALVIGNAC JEAN LOUIS , VERPLANKEN FABRICE JEAN , HEDDES MARCO C , JENKINS STEVEN KENNETH , TROMBLEY MICHAEL RAYMOND , SIEGEL MICHAEL STEVEN , BASS BRIAN MITCHELL
IPC: G06F12/06 , G06F12/00 , G06F12/02 , G06F13/00 , G06F13/16 , G06F15/167 , G11C11/407 , H04L12/56 , G11C7/10
Abstract: The ability of network processors to move data to and from dynamic random access memory (DRAM) chips used in computer systems is enhanced in several respects. In on e aspect of the invention, two double data rate DRAMS are used in parallel to double the bandwidth for increased throughput of data. The movement of data is further improved by setting 4 banks of full 'read' and 4 banks of full 'write' by the network processor for every repetition of the DRAM time clock. A scheme for randomized 'read' and 'write' access by the network processor is disclosed. This scheme is particularly applicable to networks such as Ethernet that utilize variabl e frame sizes.
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公开(公告)号：PL355786A1
公开(公告)日：2004-05-17
申请号：PL35578600
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVID GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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公开(公告)号：CZ20021442A3
公开(公告)日：2002-07-17
申请号：CZ20021442
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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