Abstract:
A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
Abstract:
Methods, apparatus and program products for controlling a flow of a plurality of packets in a computer network are disclosed. The computer network includes a device defining a queue. The methods, apparatus and program products include determining a queue level for the queue and determining an offered rate of the plurality of packets to the queue. They also include controlling a transmission fraction of the plurality of packets to or from the queue, based on the queue level, the offered rate and a previous value of the transmission fraction so that the transmission fraction and the queue level are critically damped if the queue level is between at least a first queue level and a second queue level. Several embodiments are disclosed in which various techniques are used to determine the manner of the control.
Abstract:
A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.
Abstract:
A network switching apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors (12) and a suite of peripheral elements formed on a semiconductor substrate (10). The interface processors (12) and peripherals together form a network processor capable of cooperating with other elements including an optional switch fabric device in executing instructions directing the flow of data in the network.
Abstract:
A network processor (10) useful in network switch apparatus and methods of operating such a processor (10) in which data flow handling and flexibility is enhanced by the cooperation of a plurality of interface processors (16, 34) formed on a semiconductor substrate. The interface processors (16, 34) provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate.
Abstract:
A network processor (10) useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of an embedded processor complex (12) with a suite of peripherals (14-36 and 40), all formed on a common semiconductor substrate. The interface processors (16, 34) provide data path for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate, while storage of transiting data flow portions is provided by memory peripherals and interfaces to external memory elements.
Abstract:
A network switch apparatus (10), components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate (10). The memory elements and interface processors together form a network processor (10) capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by a plurality of processors.
Abstract:
PROBLEM TO BE SOLVED: To improve the capacity of a network processor for moving data to a dynamic random access memory(DRAM) chip to be used for a computer system or moving data from the chip. SOLUTION: Two double data rate DRAMs are used in order to double band width in accordance with the throughput of increased data. The movement of data is further improved by setting up complete reading of four banks and complete writing of four banks by a network processor in each repeat of a DRAM time clock. A scheme for reading and writing accesses randomized by the network processor is discloses. The scheme can be applied especially to a network such as the Ethernet (R) using various frame sizes.
Abstract:
PROBLEM TO BE SOLVED: To provide a bandwidth maintenance queue manager for (first-in first-out)FIFO buffer provided with another DRAM storage device for maintaining a FIFO queue. SOLUTION: A FIFO buffer is used on an ASIC chip so that plural queue entries can be stored and retrieved. As long as the total size of queues does not exceed a usable storage device in the buffer, any data storage device is not required more. When supplied data exceeds the buffer storage space of a certain prescribed quantity in the FIFO buffer, however, these data are written in the other data storage device in the form of packet and read from that storage device. That packet has an optimal size for maintaining the peak performance of the data storage device and is written in the data storage device in a way such as queuing with the address sequence of FIFO.
Abstract:
PROBLEM TO BE SOLVED: To provide a scalable switch architecture which is used in data communication network, increases processing speed of transferred data, and can resize support capability into within a scope of each type of potential request. SOLUTION: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network. COPYRIGHT: (C)2006,JPO&NCIPI